1 /* 2 * Copyright (c) 2008 The DragonFly Project. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 3. Neither the name of The DragonFly Project nor the names of its 15 * contributors may be used to endorse or promote products derived 16 * from this software without specific, prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 22 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $DragonFly: src/sys/dev/netif/sln/if_slnreg.h,v 1.1 2008/02/28 18:39:20 swildner Exp $ 32 */ 33 34 #ifndef _IF_SLREG_H_ 35 #define _IF_SLREG_H_ 36 37 /* 38 * Silan netcard register offsets 39 */ 40 41 #define SL_CFG0 0x00 /* software reset */ 42 #define SL_CFG1 0x04 /* select RX buffer size */ 43 #define SL_RBW_PTR 0x08 /* RX buffer write pointer */ 44 #define SL_INT_STATUS 0x0C /* interrupt status register */ 45 #define SL_INT_MASK 0x10 /* interrupt mask register */ 46 #define SL_RBSA 0x14 /* RX buffer start address */ 47 #define SL_RBR_PTR 0x18 /* RX buffer read pointer */ 48 #define SL_TSALD0 0x1C /* TX status of all descriptors */ 49 #define SL_TSD0 0x20 /* TX status of descriptor 0 */ 50 #define SL_TSD1 0x24 /* TX status of descriptor 1 */ 51 #define SL_TSD2 0x28 /* TX status of descriptor 2 */ 52 #define SL_TSD3 0x2C /* TX status of descriptor 3 */ 53 #define SL_TSAD0 0x30 /* TX start address of descriptor 0 */ 54 #define SL_TSAD1 0x34 /* TX start address of descriptor 1 */ 55 #define SL_TSAD2 0x38 /* TX start address of descriptor 2 */ 56 #define SL_TSAD3 0x3C /* TX start address of descriptor 3 */ 57 #define SL_RX_CONFIG 0x40 /* RX configuration register */ 58 #define SL_MAC_ADDR0 0x44 /* MAC address register 0 [47-16] */ 59 #define SL_MAC_ADDR1 0x48 /* MAC address register 1 [15-0] */ 60 #define SL_MULTI_GROUP0 0x4C /* multicast address config regiser 0 [63-32] */ 61 #define SL_MULTI_GROUP1 0x50 /* multicast address config regiser 1 [31-0] */ 62 #define SL_RX_STATUS0 0x54 /* RX status register 0 */ 63 /* 0x58 reserved */ 64 #define SL_TX_CONFIG 0x5C /* TX configuration register */ 65 #define SL_PHY_CTRL 0x60 /* Physical control */ 66 #define SL_FLOW_CTRL 0x64 /* flow control register */ 67 #define SL_MII_CMD0 0x68 /* MII command register 0 */ 68 #define SL_MII_CMD1 0x6C /* MII command register 1 */ 69 #define SL_MII_STATUS 0x70 /* MII status register */ 70 #define SL_TIMER_CNT 0x74 /* Timer counter register */ 71 #define SL_TIMER_INTR 0x78 /* TImer interrupt register */ 72 #define SL_PM_CFG 0x7C /* power managerment configuration register */ 73 74 /* config register 0 */ 75 #define SL_SOFT_RESET 0x80000000 76 #define SL_ANAOFF 0x40000000 77 #define SL_LDPS 0x20000000 78 79 /* config register 1 */ 80 #define SL_EARLY_RX 0x80000000 81 #define SL_EARLY_TX 0x40000000 82 83 #define SL_RXFIFO_16BYTES 0x00000000 84 #define SL_RXFIFO_32BYTES 0x00200000 85 #define SL_RXFIFO_64BYTES 0x00400000 86 #define SL_RXFIFO_128BYTES 0x00600000 87 #define SL_RXFIFO_256BYTES 0x00800000 88 #define SL_RXFIFO_512BYTES 0x00A00000 89 #define SL_RXFIFO_1024BYTES 0x00C00000 90 #define SL_RXFIFO_NOTHRESH 0x00E00000 91 92 #define SL_RXBUF_8 0x00000000 93 #define SL_RXBUF_16 0x00000001 94 #define SL_RXBUF_32 0x00000003 95 #define SL_RXBUF_64 0x00000007 96 #define SL_RXBUF_128 0x0000000F 97 98 /* interrupt status register bits */ 99 #define SL_INT_LINKFAIL 0x80000000 100 #define SL_INT_LINKOK 0x40000000 101 #define SL_INT_TIMEOUT 0x20000000 102 #define SL_INT_DMARD_ST 0x00080000 103 #define SL_INT_DMARD_FIN 0x00040000 104 #define SL_INT_STB_Pl 0x00020000 105 #define SL_INT_TXFIN_P 0x00010000 106 #define SL_INT_RXFIN_P 0x00008000 107 #define SL_INT_DMAWR_ST 0x00004000 108 #define SL_INT_DMAWR_FIN 0x00002000 109 #define SL_INT_RBO 0x00000040 110 #define SL_INT_ROK 0x00000020 111 #define SL_INT_TOK 0x00000001 112 113 #define SL_INRTS (SL_INT_LINKFAIL | SL_INT_LINKOK | SL_INT_TIMEOUT | SL_INT_RBO | SL_INT_ROK | SL_INT_TOK) 114 115 /* TX status of silan descriptors */ 116 #define SL_TXSAD_TOK3 0x00008000 117 #define SL_TXSAD_TOK2 0x00004000 118 #define SL_TXSAD_TOK1 0x00002000 119 #define SL_TXSAD_TOK0 0x00001000 120 #define SL_TXSAD_TUN3 0x00000800 121 #define SL_TXSAD_TUN2 0x00000400 122 #define SL_TXSAD_TUN1 0x00000200 123 #define SL_TXSAD_TUN0 0x00000100 124 #define SL_TXSAD_TABT3 0x00000080 125 #define SL_TXSAD_TABT2 0x00000040 126 #define SL_TXSAD_TABT1 0x00000020 127 #define SL_TXSAD_TABT0 0x00000010 128 #define SL_TXSAD_OWN3 0x00000008 129 #define SL_TXSAD_OWN2 0x00000004 130 #define SL_TXSAD_OWN1 0x00000002 131 #define SL_TXSAD_OWN0 0x00000001 132 133 /* Transmit descriptor status register bits */ 134 #define SL_TXSD_CRS 0x20000000 135 #define SL_TXSD_TABT 0x10000000 136 #define SL_TXSD_OWC 0x08000000 137 #define SL_TXSD_NCC 0x03C00000 138 #define SL_TXSD_EARLY_THRESH 0x003F0000 139 #define SL_TXSD_TOK 0x00008000 140 #define SL_TXSD_TUN 0x00004000 141 #define SL_TXSD_OWN 0x00002000 142 #define SL_TXSD_LENMASK 0x00001FFF 143 144 /* bits in TX configuration register */ 145 #define SL_TXCFG_FULLDX 0x80000000 146 #define SL_TXCFG_EN 0x40000000 147 #define SL_TXCFG_PAD 0x20000000 148 #define SL_TXCFG_HUGE 0x10000000 149 #define SL_TXCFG_FCS 0x08000000 150 #define SL_TXCFG_NOBACKOFF 0x04000000 151 #define SL_TXCFG_PREMBLE 0x02000000 152 #define SL_TXCFG_LOSTCRS 0x01000000 153 #define SL_TXCFG_EXDCOLLNUM 0x00F00000 154 #define SL_TXCFG_DATARATE 0x00080000 155 156 /* bits in RX configuration register */ 157 #define SL_RXCFG_FULLDX 0x80000000 158 #define SL_RXCFG_EN 0x40000000 159 #define SL_RXCFG_RCV_SMALL 0x20000000 160 #define SL_RXCFG_RCV_HUGE 0x10000000 161 #define SL_RXCFG_RCV_ERR 0x08000000 162 #define SL_RXCFG_RCV_ALL 0x04000000 163 #define SL_RXCFG_RCV_MULTI 0x02000000 164 #define SL_RXCFG_RCV_BROAD 0x01000000 165 #define SL_RXCFG_LP_BCK 0x00C00000 166 #define SL_RXCFG_LOW_THRESHOLD 0x00040000 167 #define SL_RXCFG_HIGH_THRESHOLD 0x00000700 168 169 /* Bits in RX status header (in RX'ed packet) */ 170 #define SL_RXSTAT_LENMASK 0xFFF00000 171 #define SL_RXSTAT_RXOK 0x00080000 172 #define SL_RXSTAT_ALIGNERR 0x00040000 173 #define SL_RXSTAT_HUGEFRM 0x00020000 174 #define SL_RXSTAT_SMALLFRM 0x00010000 175 #define SL_RXSTAT_CRCOK 0x00008000 176 #define SL_RXSTAT_CRLFRM 0x00004000 177 #define SL_RXSTAT_BROAD 0x00002000 178 #define SL_RXSTAT_MULTI 0x00001000 179 #define SL_RXSTAT_MATCH 0x00000800 180 #define SL_RXSTAT_MIIERR 0x00000400 181 182 /* Physical Control configuration register */ 183 #define SL_PHYCTL_ANE 0x80000000 184 #define SL_PHYCTL_SPD100 0x40000000 185 #define SL_PHYCTL_SPD10 0x20000000 186 #define SL_PHYCTL_BASEADD 0x1F000000 187 #define SL_PHYCTL_DUX 0x00800000 188 #define SL_PHYCTL_RESET 0x00400000 189 190 /* Flow Control configuration register */ 191 #define SL_FLOWCTL_FULLDX 0x80000000 192 #define SL_FLOWCTL_EN 0x40000000 193 #define SL_FLOWCTL_PASSALL 0x20000000 194 #define SL_FLOWCTL_ENPAUSE 0x10000000 195 #define SL_FLOWCTL_PAUSEF 0x08000000 196 #define SL_FLOWCTL_PAUSE0 0x04000000 197 198 /* MII command register 0 */ 199 #define SL_MII0_DIVEDER 0x20000000 200 #define SL_MII0_NOPRE 0x00800000 201 #define SL_MII0_WRITE 0x00400000 202 #define SL_MII0_READ 0x00200000 203 #define SL_MII0_SCAN 0x00100000 204 #define SL_MII0_TXMODE 0x00080000 205 #define SL_MII0_DRVMOD 0x00040000 206 #define SL_MII0_MDC 0x00020000 207 #define SL_MII0_MDOEN 0x00010000 208 #define SL_MII0_MDO 0x00008000 209 #define SL_MII0_MDI 0x00004000 210 211 /* MII status register */ 212 #define SL_MIISTAT_BUSY 0x80000000 213 214 /* register in 80225 */ 215 #define SL_MII_CTRL 0 216 #define SL_MII_STAT 1 217 #define SL_MII_ADV 4 218 #define SL_MII_JAB 16 219 #define SL_MII_STAT_OUTPUT 24 220 221 /* bit value for 80225 */ 222 #define SL_MIICTRL_ANEGEN 0x1000 223 #define SL_MIICTRL_SPEEDSEL 0x2000 224 #define SL_MIICTRL_DUPSEL 0x0100 225 #define SL_MIICTRL_ANEGRSTR 0x0200 226 #define SL_MIISTAT_LINK 0x0004 227 #define SL_MIISTAT_ANEGACK 0x0020 228 #define SL_PHY_16_JAB_ENB 0x1000 229 #define SL_PHY_16_PORT_ENB 0x1 230 231 /* 232 * PCI low memory base and low I/O base register, and other PCI registers. 233 */ 234 #define SL_PCI_VENDORID 0x00 235 #define SL_PCI_DEVICEID 0x02 236 #define SL_PCI_COMMAND 0x04 237 #define SL_PCI_STATUS 0x06 238 #define SL_PCI_REVISIONID 0x08 239 #define SL_PCI_MEMAD 0x10 240 #define SL_PCI_IOAD 0x14 241 #define SL_PCI_SUBVENDORID 0x2C 242 #define SL_PCI_SUBDEVICEID 0x2E 243 #define RL_PCI_INTLINE 0x3C 244 245 #define SL_CMD_IO 0x0001 246 #define SL_CMD_MEMORY 0x0002 247 #define SL_CMD_BUSMASTER 0x0004 248 249 #define SL_TXD_CNT 4 250 #define SL_RX_BUF_SZ SL_RXBUF_64 251 #define SL_RX_BUFLEN (1 << (SL_RX_BUF_SZ + 9)) 252 #define TX_CFG_DEFAULT 0x48800000 253 254 /* register space access macros */ 255 #define SLN_WRITE_4(adapter, reg, val) bus_space_write_4(adapter->sln_bustag, adapter->sln_bushandle, reg, val) 256 #define SLN_WRITE_2(adapter, reg, val) bus_space_write_2(adapter->sln_bustag, adapter->sln_bushandle, reg, val) 257 #define SLN_WRITE_1(adapter, reg, val) bus_space_write_1(adapter->sln_bustag, adapter->sln_bushandle, reg, val) 258 259 #define SLN_READ_4(adapter, reg) bus_space_read_4(adapter->sln_bustag, adapter->sln_bushandle, reg) 260 #define SLN_READ_2(adapter, reg) bus_space_read_2(adapter->sln_bustag, adapter->sln_bushandle, reg) 261 #define SLN_READ_1(adapter, reg) bus_space_read_1(adapter->sln_bustag, adapter->sln_bushandle, reg) 262 263 #define SL_DIRTY_TXBUF(x) x->sln_bufdata.sln_tx_buf[x->sln_bufdata.dirty_tx] 264 #define SL_CUR_TXBUF(x) x->sln_bufdata.sln_tx_buf[x->sln_bufdata.cur_tx] 265 266 #endif /* !_IF_SLREG_H_ */ 267