Home
last modified time | relevance | path

Searched refs:SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_1_sh_mask.h3600 #define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 macro
H A Dsmu_7_1_0_sh_mask.h3598 #define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 macro
H A Dsmu_7_1_2_sh_mask.h3760 #define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 macro
H A Dsmu_7_1_3_sh_mask.h3428 #define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 macro