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Searched refs:SPI_CDBG_SYS_CS1__PIPE0_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h8827 #define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff macro
H A Dgfx_8_0_sh_mask.h10429 #define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff macro
H A Dgfx_8_1_sh_mask.h10827 #define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12147 #define SPI_CDBG_SYS_CS1__PIPE0_MASK … macro
H A Dgc_9_2_1_sh_mask.h13452 #define SPI_CDBG_SYS_CS1__PIPE0_MASK … macro