Home
last modified time | relevance | path

Searched refs:SPI_COMPUTE_QUEUE_RESET__RESET_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h8899 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h10519 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h10917 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12275 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK … macro
H A Dgc_9_1_sh_mask.h13704 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK … macro
H A Dgc_9_2_1_sh_mask.h13569 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK … macro