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Searched refs:SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7478 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L macro
H A Dgfx_7_2_sh_mask.h9249 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 macro
H A Dgfx_8_0_sh_mask.h10969 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 macro
H A Dgfx_8_1_sh_mask.h11367 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h20252 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK … macro
H A Dgc_9_1_sh_mask.h21688 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK … macro
H A Dgc_9_2_1_sh_mask.h21618 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK … macro