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Searched refs:SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h11085 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff macro
H A Dgfx_8_0_sh_mask.h12811 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff macro
H A Dgfx_8_1_sh_mask.h13209 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h4353 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
H A Dgc_9_1_sh_mask.h3932 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
H A Dgc_9_2_1_sh_mask.h3838 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro