Home
last modified time | relevance | path

Searched refs:SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h8871 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 macro
H A Dgfx_8_0_sh_mask.h10491 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 macro
H A Dgfx_8_1_sh_mask.h10889 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12214 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK … macro
H A Dgc_9_2_1_sh_mask.h13519 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK … macro