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Searched refs:SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12248 #define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK … macro
H A Dgc_9_2_1_sh_mask.h13553 #define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK … macro