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Searched refs:SPI_GDBG_WAVE_CNTL__STALL_RA_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h8855 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h10473 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h10871 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12196 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_9_2_1_sh_mask.h13501 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro