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Searched refs:SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7666 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000f0L macro
H A Dgfx_7_2_sh_mask.h9209 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 macro
H A Dgfx_8_0_sh_mask.h10929 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 macro
H A Dgfx_8_1_sh_mask.h11327 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h21512 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK … macro
H A Dgc_9_1_sh_mask.h22948 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK … macro
H A Dgc_9_2_1_sh_mask.h22915 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK … macro