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Searched refs:SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7680 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0f000000L macro
H A Dgfx_7_2_sh_mask.h9219 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 macro
H A Dgfx_8_0_sh_mask.h10939 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 macro
H A Dgfx_8_1_sh_mask.h11337 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h21517 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK … macro
H A Dgc_9_1_sh_mask.h22953 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK … macro
H A Dgc_9_2_1_sh_mask.h22920 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK … macro