Home
last modified time | relevance | path

Searched refs:SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h10161 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000 macro
H A Dgfx_8_1_sh_mask.h10559 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16054 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK … macro
H A Dgc_9_1_sh_mask.h17488 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK … macro
H A Dgc_9_2_1_sh_mask.h17363 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK … macro