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Searched refs:SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h9001 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf macro
H A Dgfx_8_0_sh_mask.h10621 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf macro
H A Dgfx_8_1_sh_mask.h11019 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12482 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK … macro
H A Dgc_9_1_sh_mask.h13911 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK … macro
H A Dgc_9_2_1_sh_mask.h13776 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK … macro