Home
last modified time | relevance | path

Searched refs:SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h8952 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h10572 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h10970 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12332 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT … macro
H A Dgc_9_1_sh_mask.h13761 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h13626 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT … macro