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Searched refs:SPLL_CNTL_MODE__SPLL_ENSAT_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_sh_mask.h290 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x00000010L macro
H A Dsmu_7_0_0_sh_mask.h215 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 macro
H A Dsmu_7_1_1_sh_mask.h205 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 macro
H A Dsmu_7_0_1_sh_mask.h205 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 macro
H A Dsmu_7_1_0_sh_mask.h205 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 macro
H A Dsmu_7_1_2_sh_mask.h205 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 macro
H A Dsmu_7_1_3_sh_mask.h231 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 macro