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Searched refs:SPLL_CTLREQ_CHG (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dsid.h97 #define SPLL_CTLREQ_CHG (1 << 23) macro
H A Dsi.c3982 tmp |= SPLL_CTLREQ_CHG; in si_set_clk_bypass_mode()
3992 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE); in si_set_clk_bypass_mode()