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Searched refs:SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h3617 #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT … macro
H A Dgc_9_1_sh_mask.h3566 #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT … macro