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Searched refs:SQ_EDC_INFO__SIMD_ID__SHIFT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h14082 #define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 macro
H A Dgfx_8_1_sh_mask.h14480 #define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h3120 #define SQ_EDC_INFO__SIMD_ID__SHIFT … macro
H A Dgc_9_1_sh_mask.h3069 #define SQ_EDC_INFO__SIMD_ID__SHIFT … macro