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Searched refs:SQ_IND_INDEX__SIMD_ID__SHIFT (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c1094 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1106 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
H A Dgfx_v8_0.c5493 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
5505 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h9011 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x00000004 macro
H A Dgfx_7_2_sh_mask.h12402 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 macro
H A Dgfx_8_0_sh_mask.h14272 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 macro
H A Dgfx_8_1_sh_mask.h14670 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h2520 #define SQ_IND_INDEX__SIMD_ID__SHIFT … macro
H A Dgc_9_1_sh_mask.h2469 #define SQ_IND_INDEX__SIMD_ID__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h2427 #define SQ_IND_INDEX__SIMD_ID__SHIFT … macro