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Searched refs:SQ_SOP2__ENCODING_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h9496 #define SQ_SOP2__ENCODING_MASK 0xc0000000L macro
H A Dgfx_7_2_sh_mask.h12941 #define SQ_SOP2__ENCODING_MASK 0xc0000000 macro
H A Dgfx_8_0_sh_mask.h14825 #define SQ_SOP2__ENCODING_MASK 0xc0000000 macro
H A Dgfx_8_1_sh_mask.h15223 #define SQ_SOP2__ENCODING_MASK 0xc0000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h2817 #define SQ_SOP2__ENCODING_MASK … macro
H A Dgc_9_1_sh_mask.h2766 #define SQ_SOP2__ENCODING_MASK … macro
H A Dgc_9_2_1_sh_mask.h2724 #define SQ_SOP2__ENCODING_MASK … macro