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Searched refs:SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h9901 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x00000000 macro
H A Dgfx_7_2_sh_mask.h12450 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h14320 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h14718 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28384 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT … macro
H A Dgc_9_1_sh_mask.h29724 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h30052 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT … macro