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Searched refs:STEP_0_SPLL_FB_DIV_MASK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dr600_dpm.c497 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK); in r600_engine_clock_entry_set_feedback_divider()
H A Dr600d.h1366 # define STEP_0_SPLL_FB_DIV_MASK (0xff << 8) macro