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Searched refs:SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h10322 #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x00008000L macro
H A Dgfx_7_2_sh_mask.h7307 #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 macro
H A Dgfx_8_0_sh_mask.h8095 #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 macro
H A Dgfx_8_1_sh_mask.h8649 #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 macro