1 /* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 4 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 Under Section 7 of GPL version 3, you are granted additional 19 permissions described in the GCC Runtime Library Exception, version 20 3.1, as published by the Free Software Foundation. 21 22 You should have received a copy of the GNU General Public License and 23 a copy of the GCC Runtime Library Exception along with this program; 24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 25 <http://www.gnu.org/licenses/>. */ 26 27 /* The purpose of this file is to define the characteristics of the i386, 28 independent of assembler syntax or operating system. 29 30 Three other files build on this one to describe a specific assembler syntax: 31 bsd386.h, att386.h, and sun386.h. 32 33 The actual tm.h file for a particular system should include 34 this file, and then the file for the appropriate assembler syntax. 35 36 Many macros that specify assembler syntax are omitted entirely from 37 this file because they really belong in the files for particular 38 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 39 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 40 that start with ASM_ or end in ASM_OP. */ 41 42 /* Redefines for option macros. */ 43 44 #define TARGET_64BIT OPTION_ISA_64BIT 45 #define TARGET_X32 OPTION_ISA_X32 46 #define TARGET_MMX OPTION_ISA_MMX 47 #define TARGET_3DNOW OPTION_ISA_3DNOW 48 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A 49 #define TARGET_SSE OPTION_ISA_SSE 50 #define TARGET_SSE2 OPTION_ISA_SSE2 51 #define TARGET_SSE3 OPTION_ISA_SSE3 52 #define TARGET_SSSE3 OPTION_ISA_SSSE3 53 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1 54 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2 55 #define TARGET_AVX OPTION_ISA_AVX 56 #define TARGET_AVX2 OPTION_ISA_AVX2 57 #define TARGET_FMA OPTION_ISA_FMA 58 #define TARGET_SSE4A OPTION_ISA_SSE4A 59 #define TARGET_FMA4 OPTION_ISA_FMA4 60 #define TARGET_XOP OPTION_ISA_XOP 61 #define TARGET_LWP OPTION_ISA_LWP 62 #define TARGET_ROUND OPTION_ISA_ROUND 63 #define TARGET_ABM OPTION_ISA_ABM 64 #define TARGET_BMI OPTION_ISA_BMI 65 #define TARGET_BMI2 OPTION_ISA_BMI2 66 #define TARGET_LZCNT OPTION_ISA_LZCNT 67 #define TARGET_TBM OPTION_ISA_TBM 68 #define TARGET_POPCNT OPTION_ISA_POPCNT 69 #define TARGET_SAHF OPTION_ISA_SAHF 70 #define TARGET_MOVBE OPTION_ISA_MOVBE 71 #define TARGET_CRC32 OPTION_ISA_CRC32 72 #define TARGET_AES OPTION_ISA_AES 73 #define TARGET_PCLMUL OPTION_ISA_PCLMUL 74 #define TARGET_CMPXCHG16B OPTION_ISA_CX16 75 #define TARGET_FSGSBASE OPTION_ISA_FSGSBASE 76 #define TARGET_RDRND OPTION_ISA_RDRND 77 #define TARGET_F16C OPTION_ISA_F16C 78 79 #define TARGET_LP64 (TARGET_64BIT && !TARGET_X32) 80 81 /* SSE4.1 defines round instructions */ 82 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 83 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) 84 85 #include "config/vxworks-dummy.h" 86 87 #include "config/i386/i386-opts.h" 88 89 #define MAX_STRINGOP_ALGS 4 90 91 /* Specify what algorithm to use for stringops on known size. 92 When size is unknown, the UNKNOWN_SIZE alg is used. When size is 93 known at compile time or estimated via feedback, the SIZE array 94 is walked in order until MAX is greater then the estimate (or -1 95 means infinity). Corresponding ALG is used then. 96 For example initializer: 97 {{256, loop}, {-1, rep_prefix_4_byte}} 98 will use loop for blocks smaller or equal to 256 bytes, rep prefix will 99 be used otherwise. */ 100 struct stringop_algs 101 { 102 const enum stringop_alg unknown_size; 103 const struct stringop_strategy { 104 const int max; 105 const enum stringop_alg alg; 106 } size [MAX_STRINGOP_ALGS]; 107 }; 108 109 /* Define the specific costs for a given cpu */ 110 111 struct processor_costs { 112 const int add; /* cost of an add instruction */ 113 const int lea; /* cost of a lea instruction */ 114 const int shift_var; /* variable shift costs */ 115 const int shift_const; /* constant shift costs */ 116 const int mult_init[5]; /* cost of starting a multiply 117 in QImode, HImode, SImode, DImode, TImode*/ 118 const int mult_bit; /* cost of multiply per each bit set */ 119 const int divide[5]; /* cost of a divide/mod 120 in QImode, HImode, SImode, DImode, TImode*/ 121 int movsx; /* The cost of movsx operation. */ 122 int movzx; /* The cost of movzx operation. */ 123 const int large_insn; /* insns larger than this cost more */ 124 const int move_ratio; /* The threshold of number of scalar 125 memory-to-memory move insns. */ 126 const int movzbl_load; /* cost of loading using movzbl */ 127 const int int_load[3]; /* cost of loading integer registers 128 in QImode, HImode and SImode relative 129 to reg-reg move (2). */ 130 const int int_store[3]; /* cost of storing integer register 131 in QImode, HImode and SImode */ 132 const int fp_move; /* cost of reg,reg fld/fst */ 133 const int fp_load[3]; /* cost of loading FP register 134 in SFmode, DFmode and XFmode */ 135 const int fp_store[3]; /* cost of storing FP register 136 in SFmode, DFmode and XFmode */ 137 const int mmx_move; /* cost of moving MMX register. */ 138 const int mmx_load[2]; /* cost of loading MMX register 139 in SImode and DImode */ 140 const int mmx_store[2]; /* cost of storing MMX register 141 in SImode and DImode */ 142 const int sse_move; /* cost of moving SSE register. */ 143 const int sse_load[3]; /* cost of loading SSE register 144 in SImode, DImode and TImode*/ 145 const int sse_store[3]; /* cost of storing SSE register 146 in SImode, DImode and TImode*/ 147 const int mmxsse_to_integer; /* cost of moving mmxsse register to 148 integer and vice versa. */ 149 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 150 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 151 const int prefetch_block; /* bytes moved to cache for prefetch. */ 152 const int simultaneous_prefetches; /* number of parallel prefetch 153 operations. */ 154 const int branch_cost; /* Default value for BRANCH_COST. */ 155 const int fadd; /* cost of FADD and FSUB instructions. */ 156 const int fmul; /* cost of FMUL instruction. */ 157 const int fdiv; /* cost of FDIV instruction. */ 158 const int fabs; /* cost of FABS instruction. */ 159 const int fchs; /* cost of FCHS instruction. */ 160 const int fsqrt; /* cost of FSQRT instruction. */ 161 /* Specify what algorithm 162 to use for stringops on unknown size. */ 163 struct stringop_algs memcpy[2], memset[2]; 164 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding 165 load and store. */ 166 const int scalar_load_cost; /* Cost of scalar load. */ 167 const int scalar_store_cost; /* Cost of scalar store. */ 168 const int vec_stmt_cost; /* Cost of any vector operation, excluding 169 load, store, vector-to-scalar and 170 scalar-to-vector operation. */ 171 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ 172 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ 173 const int vec_align_load_cost; /* Cost of aligned vector load. */ 174 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ 175 const int vec_store_cost; /* Cost of vector store. */ 176 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 177 cost model. */ 178 const int cond_not_taken_branch_cost;/* Cost of not taken branch for 179 vectorizer cost model. */ 180 }; 181 182 extern const struct processor_costs *ix86_cost; 183 extern const struct processor_costs ix86_size_cost; 184 185 #define ix86_cur_cost() \ 186 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 187 188 /* Macros used in the machine description to test the flags. */ 189 190 /* configure can arrange to make this 2, to force a 486. */ 191 192 #ifndef TARGET_CPU_DEFAULT 193 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic 194 #endif 195 196 #ifndef TARGET_FPMATH_DEFAULT 197 #define TARGET_FPMATH_DEFAULT \ 198 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 199 #endif 200 201 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 202 203 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 204 compile-time constant. */ 205 #ifdef IN_LIBGCC2 206 #undef TARGET_64BIT 207 #ifdef __x86_64__ 208 #define TARGET_64BIT 1 209 #else 210 #define TARGET_64BIT 0 211 #endif 212 #else 213 #ifndef TARGET_BI_ARCH 214 #undef TARGET_64BIT 215 #if TARGET_64BIT_DEFAULT 216 #define TARGET_64BIT 1 217 #else 218 #define TARGET_64BIT 0 219 #endif 220 #endif 221 #endif 222 223 #define HAS_LONG_COND_BRANCH 1 224 #define HAS_LONG_UNCOND_BRANCH 1 225 226 #define TARGET_386 (ix86_tune == PROCESSOR_I386) 227 #define TARGET_486 (ix86_tune == PROCESSOR_I486) 228 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 229 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 230 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 231 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) 232 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 233 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 234 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) 235 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 236 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 237 #define TARGET_CORE2_32 (ix86_tune == PROCESSOR_CORE2_32) 238 #define TARGET_CORE2_64 (ix86_tune == PROCESSOR_CORE2_64) 239 #define TARGET_CORE2 (TARGET_CORE2_32 || TARGET_CORE2_64) 240 #define TARGET_COREI7_32 (ix86_tune == PROCESSOR_COREI7_32) 241 #define TARGET_COREI7_64 (ix86_tune == PROCESSOR_COREI7_64) 242 #define TARGET_COREI7 (TARGET_COREI7_32 || TARGET_COREI7_64) 243 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) 244 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) 245 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) 246 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 247 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) 248 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) 249 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) 250 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) 251 252 /* Feature tests against the various tunings. */ 253 enum ix86_tune_indices { 254 X86_TUNE_USE_LEAVE, 255 X86_TUNE_PUSH_MEMORY, 256 X86_TUNE_ZERO_EXTEND_WITH_AND, 257 X86_TUNE_UNROLL_STRLEN, 258 X86_TUNE_BRANCH_PREDICTION_HINTS, 259 X86_TUNE_DOUBLE_WITH_ADD, 260 X86_TUNE_USE_SAHF, 261 X86_TUNE_MOVX, 262 X86_TUNE_PARTIAL_REG_STALL, 263 X86_TUNE_PARTIAL_FLAG_REG_STALL, 264 X86_TUNE_USE_HIMODE_FIOP, 265 X86_TUNE_USE_SIMODE_FIOP, 266 X86_TUNE_USE_MOV0, 267 X86_TUNE_USE_CLTD, 268 X86_TUNE_USE_XCHGB, 269 X86_TUNE_SPLIT_LONG_MOVES, 270 X86_TUNE_READ_MODIFY_WRITE, 271 X86_TUNE_READ_MODIFY, 272 X86_TUNE_PROMOTE_QIMODE, 273 X86_TUNE_FAST_PREFIX, 274 X86_TUNE_SINGLE_STRINGOP, 275 X86_TUNE_QIMODE_MATH, 276 X86_TUNE_HIMODE_MATH, 277 X86_TUNE_PROMOTE_QI_REGS, 278 X86_TUNE_PROMOTE_HI_REGS, 279 X86_TUNE_SINGLE_POP, 280 X86_TUNE_DOUBLE_POP, 281 X86_TUNE_SINGLE_PUSH, 282 X86_TUNE_DOUBLE_PUSH, 283 X86_TUNE_INTEGER_DFMODE_MOVES, 284 X86_TUNE_PARTIAL_REG_DEPENDENCY, 285 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, 286 X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, 287 X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, 288 X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, 289 X86_TUNE_SSE_SPLIT_REGS, 290 X86_TUNE_SSE_TYPELESS_STORES, 291 X86_TUNE_SSE_LOAD0_BY_PXOR, 292 X86_TUNE_MEMORY_MISMATCH_STALL, 293 X86_TUNE_PROLOGUE_USING_MOVE, 294 X86_TUNE_EPILOGUE_USING_MOVE, 295 X86_TUNE_SHIFT1, 296 X86_TUNE_USE_FFREEP, 297 X86_TUNE_INTER_UNIT_MOVES, 298 X86_TUNE_INTER_UNIT_CONVERSIONS, 299 X86_TUNE_FOUR_JUMP_LIMIT, 300 X86_TUNE_SCHEDULE, 301 X86_TUNE_USE_BT, 302 X86_TUNE_USE_INCDEC, 303 X86_TUNE_PAD_RETURNS, 304 X86_TUNE_PAD_SHORT_FUNCTION, 305 X86_TUNE_EXT_80387_CONSTANTS, 306 X86_TUNE_SHORTEN_X87_SSE, 307 X86_TUNE_AVOID_VECTOR_DECODE, 308 X86_TUNE_PROMOTE_HIMODE_IMUL, 309 X86_TUNE_SLOW_IMUL_IMM32_MEM, 310 X86_TUNE_SLOW_IMUL_IMM8, 311 X86_TUNE_MOVE_M1_VIA_OR, 312 X86_TUNE_NOT_UNPAIRABLE, 313 X86_TUNE_NOT_VECTORMODE, 314 X86_TUNE_USE_VECTOR_FP_CONVERTS, 315 X86_TUNE_USE_VECTOR_CONVERTS, 316 X86_TUNE_FUSE_CMP_AND_BRANCH, 317 X86_TUNE_OPT_AGU, 318 X86_TUNE_VECTORIZE_DOUBLE, 319 X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, 320 X86_TUNE_AVX128_OPTIMAL, 321 X86_TUNE_REASSOC_INT_TO_PARALLEL, 322 X86_TUNE_REASSOC_FP_TO_PARALLEL, 323 324 X86_TUNE_LAST 325 }; 326 327 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; 328 329 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 330 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 331 #define TARGET_ZERO_EXTEND_WITH_AND \ 332 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 333 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 334 #define TARGET_BRANCH_PREDICTION_HINTS \ 335 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 336 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 337 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 338 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 339 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 340 #define TARGET_PARTIAL_FLAG_REG_STALL \ 341 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 342 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 343 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 344 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 345 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 346 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 347 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 348 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 349 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 350 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 351 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 352 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 353 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 354 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 355 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 356 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 357 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] 358 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] 359 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] 360 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] 361 #define TARGET_INTEGER_DFMODE_MOVES \ 362 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 363 #define TARGET_PARTIAL_REG_DEPENDENCY \ 364 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 365 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 366 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 367 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 368 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] 369 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ 370 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] 371 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ 372 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] 373 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 374 #define TARGET_SSE_TYPELESS_STORES \ 375 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 376 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 377 #define TARGET_MEMORY_MISMATCH_STALL \ 378 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 379 #define TARGET_PROLOGUE_USING_MOVE \ 380 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 381 #define TARGET_EPILOGUE_USING_MOVE \ 382 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 383 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 384 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 385 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] 386 #define TARGET_INTER_UNIT_CONVERSIONS\ 387 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 388 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 389 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 390 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 391 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 392 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 393 #define TARGET_PAD_SHORT_FUNCTION \ 394 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] 395 #define TARGET_EXT_80387_CONSTANTS \ 396 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 397 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE] 398 #define TARGET_AVOID_VECTOR_DECODE \ 399 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 400 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 401 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 402 #define TARGET_SLOW_IMUL_IMM32_MEM \ 403 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 404 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 405 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 406 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 407 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 408 #define TARGET_USE_VECTOR_FP_CONVERTS \ 409 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 410 #define TARGET_USE_VECTOR_CONVERTS \ 411 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 412 #define TARGET_FUSE_CMP_AND_BRANCH \ 413 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] 414 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 415 #define TARGET_VECTORIZE_DOUBLE \ 416 ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE] 417 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ 418 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] 419 #define TARGET_AVX128_OPTIMAL \ 420 ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] 421 #define TARGET_REASSOC_INT_TO_PARALLEL \ 422 ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL] 423 #define TARGET_REASSOC_FP_TO_PARALLEL \ 424 ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL] 425 426 /* Feature tests against the various architecture variations. */ 427 enum ix86_arch_indices { 428 X86_ARCH_CMOV, 429 X86_ARCH_CMPXCHG, 430 X86_ARCH_CMPXCHG8B, 431 X86_ARCH_XADD, 432 X86_ARCH_BSWAP, 433 434 X86_ARCH_LAST 435 }; 436 437 extern unsigned char ix86_arch_features[X86_ARCH_LAST]; 438 439 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 440 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 441 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 442 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 443 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 444 445 /* For sane SSE instruction set generation we need fcomi instruction. 446 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic 447 expands to a sequence that includes conditional move. */ 448 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) 449 450 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 451 452 extern int x86_prefetch_sse; 453 #define TARGET_PREFETCH_SSE x86_prefetch_sse 454 455 extern int x86_prefetchw; 456 #define TARGET_PREFETCHW x86_prefetchw 457 458 #define ASSEMBLER_DIALECT (ix86_asm_dialect) 459 460 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 461 #define TARGET_MIX_SSE_I387 \ 462 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 463 464 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 465 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 466 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 467 #define TARGET_SUN_TLS 0 468 469 #ifndef TARGET_64BIT_DEFAULT 470 #define TARGET_64BIT_DEFAULT 0 471 #endif 472 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 473 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 474 #endif 475 476 /* Fence to use after loop using storent. */ 477 478 extern tree x86_mfence; 479 #define FENCE_FOLLOWING_MOVNT x86_mfence 480 481 /* Once GDB has been enhanced to deal with functions without frame 482 pointers, we can change this to allow for elimination of 483 the frame pointer in leaf functions. */ 484 #define TARGET_DEFAULT 0 485 486 /* Extra bits to force. */ 487 #define TARGET_SUBTARGET_DEFAULT 0 488 #define TARGET_SUBTARGET_ISA_DEFAULT 0 489 490 /* Extra bits to force on w/ 32-bit mode. */ 491 #define TARGET_SUBTARGET32_DEFAULT 0 492 #define TARGET_SUBTARGET32_ISA_DEFAULT 0 493 494 /* Extra bits to force on w/ 64-bit mode. */ 495 #define TARGET_SUBTARGET64_DEFAULT 0 496 #define TARGET_SUBTARGET64_ISA_DEFAULT 0 497 498 /* Replace MACH-O, ifdefs by in-line tests, where possible. 499 (a) Macros defined in config/i386/darwin.h */ 500 #define TARGET_MACHO 0 501 #define TARGET_MACHO_BRANCH_ISLANDS 0 502 #define MACHOPIC_ATT_STUB 0 503 /* (b) Macros defined in config/darwin.h */ 504 #define MACHO_DYNAMIC_NO_PIC_P 0 505 #define MACHOPIC_INDIRECT 0 506 #define MACHOPIC_PURE 0 507 508 /* For the Windows 64-bit ABI. */ 509 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 510 511 /* For the Windows 32-bit ABI. */ 512 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 513 514 /* This is re-defined by cygming.h. */ 515 #define TARGET_SEH 0 516 517 /* The default abi used by target. */ 518 #define DEFAULT_ABI SYSV_ABI 519 520 /* Subtargets may reset this to 1 in order to enable 96-bit long double 521 with the rounding mode forced to 53 bits. */ 522 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 523 524 /* -march=native handling only makes sense with compiler running on 525 an x86 or x86_64 chip. If changing this condition, also change 526 the condition in driver-i386.c. */ 527 #if defined(__i386__) || defined(__x86_64__) 528 /* In driver-i386.c. */ 529 extern const char *host_detect_local_cpu (int argc, const char **argv); 530 #define EXTRA_SPEC_FUNCTIONS \ 531 { "local_cpu_detect", host_detect_local_cpu }, 532 #define HAVE_LOCAL_CPU_DETECT 533 #endif 534 535 #if TARGET_64BIT_DEFAULT 536 #define OPT_ARCH64 "!m32" 537 #define OPT_ARCH32 "m32" 538 #else 539 #define OPT_ARCH64 "m64|mx32" 540 #define OPT_ARCH32 "m64|mx32:;" 541 #endif 542 543 /* Support for configure-time defaults of some command line options. 544 The order here is important so that -march doesn't squash the 545 tune or cpu values. */ 546 #define OPTION_DEFAULT_SPECS \ 547 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 548 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 549 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 550 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 551 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 552 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 553 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 554 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 555 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 556 557 /* Specs for the compiler proper */ 558 559 #ifndef CC1_CPU_SPEC 560 #define CC1_CPU_SPEC_1 "" 561 562 #ifndef HAVE_LOCAL_CPU_DETECT 563 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 564 #else 565 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 566 "%{march=native:%>march=native %:local_cpu_detect(arch) \ 567 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ 568 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" 569 #endif 570 #endif 571 572 /* Target CPU builtins. */ 573 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 574 575 /* Target Pragmas. */ 576 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 577 578 enum target_cpu_default 579 { 580 TARGET_CPU_DEFAULT_generic = 0, 581 582 TARGET_CPU_DEFAULT_i386, 583 TARGET_CPU_DEFAULT_i486, 584 TARGET_CPU_DEFAULT_pentium, 585 TARGET_CPU_DEFAULT_pentium_mmx, 586 TARGET_CPU_DEFAULT_pentiumpro, 587 TARGET_CPU_DEFAULT_pentium2, 588 TARGET_CPU_DEFAULT_pentium3, 589 TARGET_CPU_DEFAULT_pentium4, 590 TARGET_CPU_DEFAULT_pentium_m, 591 TARGET_CPU_DEFAULT_prescott, 592 TARGET_CPU_DEFAULT_nocona, 593 TARGET_CPU_DEFAULT_core2, 594 TARGET_CPU_DEFAULT_corei7, 595 TARGET_CPU_DEFAULT_atom, 596 597 TARGET_CPU_DEFAULT_geode, 598 TARGET_CPU_DEFAULT_k6, 599 TARGET_CPU_DEFAULT_k6_2, 600 TARGET_CPU_DEFAULT_k6_3, 601 TARGET_CPU_DEFAULT_athlon, 602 TARGET_CPU_DEFAULT_athlon_sse, 603 TARGET_CPU_DEFAULT_k8, 604 TARGET_CPU_DEFAULT_amdfam10, 605 TARGET_CPU_DEFAULT_bdver1, 606 TARGET_CPU_DEFAULT_bdver2, 607 TARGET_CPU_DEFAULT_btver1, 608 609 TARGET_CPU_DEFAULT_max 610 }; 611 612 #ifndef CC1_SPEC 613 #define CC1_SPEC "%(cc1_cpu) " 614 #endif 615 616 /* This macro defines names of additional specifications to put in the 617 specs that can be used in various specifications like CC1_SPEC. Its 618 definition is an initializer with a subgrouping for each command option. 619 620 Each subgrouping contains a string constant, that defines the 621 specification name, and a string constant that used by the GCC driver 622 program. 623 624 Do not define this macro if it does not need to do anything. */ 625 626 #ifndef SUBTARGET_EXTRA_SPECS 627 #define SUBTARGET_EXTRA_SPECS 628 #endif 629 630 #define EXTRA_SPECS \ 631 { "cc1_cpu", CC1_CPU_SPEC }, \ 632 SUBTARGET_EXTRA_SPECS 633 634 635 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the 636 FPU, assume that the fpcw is set to extended precision; when using 637 only SSE, rounding is correct; when using both SSE and the FPU, 638 the rounding precision is indeterminate, since either may be chosen 639 apparently at random. */ 640 #define TARGET_FLT_EVAL_METHOD \ 641 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 642 643 /* Whether to allow x87 floating-point arithmetic on MODE (one of 644 SFmode, DFmode and XFmode) in the current excess precision 645 configuration. */ 646 #define X87_ENABLE_ARITH(MODE) \ 647 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) 648 649 /* Likewise, whether to allow direct conversions from integer mode 650 IMODE (HImode, SImode or DImode) to MODE. */ 651 #define X87_ENABLE_FLOAT(MODE, IMODE) \ 652 (flag_excess_precision == EXCESS_PRECISION_FAST \ 653 || (MODE) == XFmode \ 654 || ((MODE) == DFmode && (IMODE) == SImode) \ 655 || (IMODE) == HImode) 656 657 /* target machine storage layout */ 658 659 #define SHORT_TYPE_SIZE 16 660 #define INT_TYPE_SIZE 32 661 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 662 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 663 #define LONG_LONG_TYPE_SIZE 64 664 #define FLOAT_TYPE_SIZE 32 665 #define DOUBLE_TYPE_SIZE 64 666 #define LONG_DOUBLE_TYPE_SIZE 80 667 668 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE 669 670 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 671 #define MAX_BITS_PER_WORD 64 672 #else 673 #define MAX_BITS_PER_WORD 32 674 #endif 675 676 /* Define this if most significant byte of a word is the lowest numbered. */ 677 /* That is true on the 80386. */ 678 679 #define BITS_BIG_ENDIAN 0 680 681 /* Define this if most significant byte of a word is the lowest numbered. */ 682 /* That is not true on the 80386. */ 683 #define BYTES_BIG_ENDIAN 0 684 685 /* Define this if most significant word of a multiword number is the lowest 686 numbered. */ 687 /* Not true for 80386 */ 688 #define WORDS_BIG_ENDIAN 0 689 690 /* Width of a word, in units (bytes). */ 691 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 692 693 #ifndef IN_LIBGCC2 694 #define MIN_UNITS_PER_WORD 4 695 #endif 696 697 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 698 #define PARM_BOUNDARY BITS_PER_WORD 699 700 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 701 #define STACK_BOUNDARY \ 702 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) 703 704 /* Stack boundary of the main function guaranteed by OS. */ 705 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 706 707 /* Minimum stack boundary. */ 708 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 709 710 /* Boundary (in *bits*) on which the stack pointer prefers to be 711 aligned; the compiler cannot rely on having this alignment. */ 712 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 713 714 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 715 both 32bit and 64bit, to support codes that need 128 bit stack 716 alignment for SSE instructions, but can't realign the stack. */ 717 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 718 719 /* 1 if -mstackrealign should be turned on by default. It will 720 generate an alternate prologue and epilogue that realigns the 721 runtime stack if nessary. This supports mixing codes that keep a 722 4-byte aligned stack, as specified by i386 psABI, with codes that 723 need a 16-byte aligned stack, as required by SSE instructions. */ 724 #define STACK_REALIGN_DEFAULT 0 725 726 /* Boundary (in *bits*) on which the incoming stack is aligned. */ 727 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 728 729 /* According to Windows x64 software convention, the maximum stack allocatable 730 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of 731 instructions allowed to adjust the stack pointer in the epilog, forcing the 732 use of frame pointer for frames larger than 2 GB. This theorical limit 733 is reduced by 256, an over-estimated upper bound for the stack use by the 734 prologue. 735 We define only one threshold for both the prolog and the epilog. When the 736 frame size is larger than this threshold, we allocate the area to save SSE 737 regs, then save them, and then allocate the remaining. There is no SEH 738 unwind info for this later allocation. */ 739 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) 740 741 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 742 mandatory for the 64-bit ABI, and may or may not be true for other 743 operating systems. */ 744 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 745 746 /* Minimum allocation boundary for the code of a function. */ 747 #define FUNCTION_BOUNDARY 8 748 749 /* C++ stores the virtual bit in the lowest bit of function pointers. */ 750 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 751 752 /* Minimum size in bits of the largest boundary to which any 753 and all fundamental data types supported by the hardware 754 might need to be aligned. No data type wants to be aligned 755 rounder than this. 756 757 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 758 and Pentium Pro XFmode values at 128 bit boundaries. */ 759 760 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256 : 128) 761 762 /* Maximum stack alignment. */ 763 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 764 765 /* Alignment value for attribute ((aligned)). It is a constant since 766 it is the part of the ABI. We shouldn't change it with -mavx. */ 767 #define ATTRIBUTE_ALIGNED_VALUE 128 768 769 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ 770 #define ALIGN_MODE_128(MODE) \ 771 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 772 773 /* The published ABIs say that doubles should be aligned on word 774 boundaries, so lower the alignment for structure fields unless 775 -malign-double is set. */ 776 777 /* ??? Blah -- this macro is used directly by libobjc. Since it 778 supports no vector modes, cut out the complexity and fall back 779 on BIGGEST_FIELD_ALIGNMENT. */ 780 #ifdef IN_TARGET_LIBS 781 #ifdef __x86_64__ 782 #define BIGGEST_FIELD_ALIGNMENT 128 783 #else 784 #define BIGGEST_FIELD_ALIGNMENT 32 785 #endif 786 #else 787 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 788 x86_field_alignment (FIELD, COMPUTED) 789 #endif 790 791 /* If defined, a C expression to compute the alignment given to a 792 constant that is being placed in memory. EXP is the constant 793 and ALIGN is the alignment that the object would ordinarily have. 794 The value of this macro is used instead of that alignment to align 795 the object. 796 797 If this macro is not defined, then ALIGN is used. 798 799 The typical use of this macro is to increase alignment for string 800 constants to be word aligned so that `strcpy' calls that copy 801 constants can be done inline. */ 802 803 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 804 805 /* If defined, a C expression to compute the alignment for a static 806 variable. TYPE is the data type, and ALIGN is the alignment that 807 the object would ordinarily have. The value of this macro is used 808 instead of that alignment to align the object. 809 810 If this macro is not defined, then ALIGN is used. 811 812 One use of this macro is to increase alignment of medium-size 813 data to make it all fit in fewer cache lines. Another is to 814 cause character arrays to be word-aligned so that `strcpy' calls 815 that copy constants to character arrays can be done inline. */ 816 817 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 818 819 /* If defined, a C expression to compute the alignment for a local 820 variable. TYPE is the data type, and ALIGN is the alignment that 821 the object would ordinarily have. The value of this macro is used 822 instead of that alignment to align the object. 823 824 If this macro is not defined, then ALIGN is used. 825 826 One use of this macro is to increase alignment of medium-size 827 data to make it all fit in fewer cache lines. */ 828 829 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 830 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 831 832 /* If defined, a C expression to compute the alignment for stack slot. 833 TYPE is the data type, MODE is the widest mode available, and ALIGN 834 is the alignment that the slot would ordinarily have. The value of 835 this macro is used instead of that alignment to align the slot. 836 837 If this macro is not defined, then ALIGN is used when TYPE is NULL, 838 Otherwise, LOCAL_ALIGNMENT will be used. 839 840 One use of this macro is to set alignment of stack slot to the 841 maximum alignment of all possible modes which the slot may have. */ 842 843 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 844 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 845 846 /* If defined, a C expression to compute the alignment for a local 847 variable DECL. 848 849 If this macro is not defined, then 850 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 851 852 One use of this macro is to increase alignment of medium-size 853 data to make it all fit in fewer cache lines. */ 854 855 #define LOCAL_DECL_ALIGNMENT(DECL) \ 856 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 857 858 /* If defined, a C expression to compute the minimum required alignment 859 for dynamic stack realignment purposes for EXP (a TYPE or DECL), 860 MODE, assuming normal alignment ALIGN. 861 862 If this macro is not defined, then (ALIGN) will be used. */ 863 864 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 865 ix86_minimum_alignment (EXP, MODE, ALIGN) 866 867 868 /* Set this nonzero if move instructions will actually fail to work 869 when given unaligned data. */ 870 #define STRICT_ALIGNMENT 0 871 872 /* If bit field type is int, don't let it cross an int, 873 and give entire struct the alignment of an int. */ 874 /* Required on the 386 since it doesn't have bit-field insns. */ 875 #define PCC_BITFIELD_TYPE_MATTERS 1 876 877 /* Standard register usage. */ 878 879 /* This processor has special stack-like registers. See reg-stack.c 880 for details. */ 881 882 #define STACK_REGS 883 884 #define IS_STACK_MODE(MODE) \ 885 (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \ 886 || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ 887 || (MODE) == XFmode) 888 889 /* Number of actual hardware registers. 890 The hardware registers are assigned numbers for the compiler 891 from 0 to just below FIRST_PSEUDO_REGISTER. 892 All registers that the compiler knows about must be given numbers, 893 even those that are not normally considered general registers. 894 895 In the 80386 we give the 8 general purpose registers the numbers 0-7. 896 We number the floating point registers 8-15. 897 Note that registers 0-7 can be accessed as a short or int, 898 while only 0-3 may be used with byte `mov' instructions. 899 900 Reg 16 does not correspond to any hardware register, but instead 901 appears in the RTL as an argument pointer prior to reload, and is 902 eliminated during reloading in favor of either the stack or frame 903 pointer. */ 904 905 #define FIRST_PSEUDO_REGISTER 53 906 907 /* Number of hardware registers that go into the DWARF-2 unwind info. 908 If not defined, equals FIRST_PSEUDO_REGISTER. */ 909 910 #define DWARF_FRAME_REGISTERS 17 911 912 /* 1 for registers that have pervasive standard uses 913 and are not available for the register allocator. 914 On the 80386, the stack pointer is such, as is the arg pointer. 915 916 The value is zero if the register is not fixed on either 32 or 917 64 bit targets, one if the register if fixed on both 32 and 64 918 bit targets, two if it is only fixed on 32bit targets and three 919 if its only fixed on 64bit targets. 920 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. 921 */ 922 #define FIXED_REGISTERS \ 923 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 924 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 925 /*arg,flags,fpsr,fpcr,frame*/ \ 926 1, 1, 1, 1, 1, \ 927 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 928 0, 0, 0, 0, 0, 0, 0, 0, \ 929 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 930 0, 0, 0, 0, 0, 0, 0, 0, \ 931 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 932 2, 2, 2, 2, 2, 2, 2, 2, \ 933 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 934 2, 2, 2, 2, 2, 2, 2, 2 } 935 936 937 /* 1 for registers not available across function calls. 938 These must include the FIXED_REGISTERS and also any 939 registers that can be used without being saved. 940 The latter must include the registers where values are returned 941 and the register where structure-value addresses are passed. 942 Aside from that, you can include as many other registers as you like. 943 944 The value is zero if the register is not call used on either 32 or 945 64 bit targets, one if the register if call used on both 32 and 64 946 bit targets, two if it is only call used on 32bit targets and three 947 if its only call used on 64bit targets. 948 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. 949 */ 950 #define CALL_USED_REGISTERS \ 951 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 952 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 953 /*arg,flags,fpsr,fpcr,frame*/ \ 954 1, 1, 1, 1, 1, \ 955 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 956 1, 1, 1, 1, 1, 1, 1, 1, \ 957 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 958 1, 1, 1, 1, 1, 1, 1, 1, \ 959 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 960 1, 1, 1, 1, 2, 2, 2, 2, \ 961 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 962 1, 1, 1, 1, 1, 1, 1, 1 } 963 964 /* Order in which to allocate registers. Each register must be 965 listed once, even those in FIXED_REGISTERS. List frame pointer 966 late and fixed registers last. Note that, in general, we prefer 967 registers listed in CALL_USED_REGISTERS, keeping the others 968 available for storage of persistent values. 969 970 The ADJUST_REG_ALLOC_ORDER actually overwrite the order, 971 so this is just empty initializer for array. */ 972 973 #define REG_ALLOC_ORDER \ 974 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 975 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 976 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 977 48, 49, 50, 51, 52 } 978 979 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 980 to be rearranged based on a particular function. When using sse math, 981 we want to allocate SSE before x87 registers and vice versa. */ 982 983 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () 984 985 986 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 987 988 /* Return number of consecutive hard regs needed starting at reg REGNO 989 to hold something of mode MODE. 990 This is ordinarily the length in words of a value of mode MODE 991 but can be less for certain modes in special long registers. 992 993 Actually there are no two word move instructions for consecutive 994 registers. And only registers 0-3 may have mov byte instructions 995 applied to them. */ 996 997 #define HARD_REGNO_NREGS(REGNO, MODE) \ 998 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 999 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1000 : ((MODE) == XFmode \ 1001 ? (TARGET_64BIT ? 2 : 3) \ 1002 : (MODE) == XCmode \ 1003 ? (TARGET_64BIT ? 4 : 6) \ 1004 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1005 1006 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 1007 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 1008 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1009 ? 0 \ 1010 : ((MODE) == XFmode || (MODE) == XCmode)) \ 1011 : 0) 1012 1013 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 1014 1015 #define VALID_AVX256_REG_MODE(MODE) \ 1016 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1017 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ 1018 || (MODE) == V4DFmode) 1019 1020 #define VALID_SSE2_REG_MODE(MODE) \ 1021 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1022 || (MODE) == V2DImode || (MODE) == DFmode) 1023 1024 #define VALID_SSE_REG_MODE(MODE) \ 1025 ((MODE) == V1TImode || (MODE) == TImode \ 1026 || (MODE) == V4SFmode || (MODE) == V4SImode \ 1027 || (MODE) == SFmode || (MODE) == TFmode) 1028 1029 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1030 ((MODE) == V2SFmode || (MODE) == SFmode) 1031 1032 #define VALID_MMX_REG_MODE(MODE) \ 1033 ((MODE == V1DImode) || (MODE) == DImode \ 1034 || (MODE) == V2SImode || (MODE) == SImode \ 1035 || (MODE) == V4HImode || (MODE) == V8QImode) 1036 1037 #define VALID_DFP_MODE_P(MODE) \ 1038 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1039 1040 #define VALID_FP_MODE_P(MODE) \ 1041 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1042 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1043 1044 #define VALID_INT_MODE_P(MODE) \ 1045 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1046 || (MODE) == DImode \ 1047 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1048 || (MODE) == CDImode \ 1049 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1050 || (MODE) == TFmode || (MODE) == TCmode))) 1051 1052 /* Return true for modes passed in SSE registers. */ 1053 #define SSE_REG_MODE_P(MODE) \ 1054 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 1055 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1056 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1057 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1058 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ 1059 || (MODE) == V2TImode) 1060 1061 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1062 1063 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1064 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1065 1066 /* Value is 1 if it is a good idea to tie two pseudo registers 1067 when one has mode MODE1 and one has mode MODE2. 1068 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1069 for any hard reg, then this must be 0 for correct output. */ 1070 1071 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 1072 1073 /* It is possible to write patterns to move flags; but until someone 1074 does it, */ 1075 #define AVOID_CCMODE_COPIES 1076 1077 /* Specify the modes required to caller save a given hard regno. 1078 We do this on i386 to prevent flags from being saved at all. 1079 1080 Kill any attempts to combine saving of modes. */ 1081 1082 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1083 (CC_REGNO_P (REGNO) ? VOIDmode \ 1084 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1085 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ 1086 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1087 : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \ 1088 : (MODE)) 1089 1090 /* The only ABI that saves SSE registers across calls is Win64 (thus no 1091 need to check the current ABI here), and with AVX enabled Win64 only 1092 guarantees that the low 16 bytes are saved. */ 1093 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 1094 (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16) 1095 1096 /* Specify the registers used for certain standard purposes. 1097 The values of these macros are register numbers. */ 1098 1099 /* on the 386 the pc register is %eip, and is not usable as a general 1100 register. The ordinary mov instructions won't work */ 1101 /* #define PC_REGNUM */ 1102 1103 /* Register to use for pushing function arguments. */ 1104 #define STACK_POINTER_REGNUM 7 1105 1106 /* Base register for access to local variables of the function. */ 1107 #define HARD_FRAME_POINTER_REGNUM 6 1108 1109 /* Base register for access to local variables of the function. */ 1110 #define FRAME_POINTER_REGNUM 20 1111 1112 /* First floating point reg */ 1113 #define FIRST_FLOAT_REG 8 1114 1115 /* First & last stack-like regs */ 1116 #define FIRST_STACK_REG FIRST_FLOAT_REG 1117 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1118 1119 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1120 #define LAST_SSE_REG (FIRST_SSE_REG + 7) 1121 1122 #define FIRST_MMX_REG (LAST_SSE_REG + 1) 1123 #define LAST_MMX_REG (FIRST_MMX_REG + 7) 1124 1125 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1126 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1127 1128 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1129 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1130 1131 /* Override this in other tm.h files to cope with various OS lossage 1132 requiring a frame pointer. */ 1133 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1134 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1135 #endif 1136 1137 /* Make sure we can access arbitrary call frames. */ 1138 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1139 1140 /* Base register for access to arguments of the function. */ 1141 #define ARG_POINTER_REGNUM 16 1142 1143 /* Register to hold the addressing base for position independent 1144 code access to data items. We don't use PIC pointer for 64bit 1145 mode. Define the regnum to dummy value to prevent gcc from 1146 pessimizing code dealing with EBX. 1147 1148 To avoid clobbering a call-saved register unnecessarily, we renumber 1149 the pic register when possible. The change is visible after the 1150 prologue has been emitted. */ 1151 1152 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG 1153 1154 #define PIC_OFFSET_TABLE_REGNUM \ 1155 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 1156 || !flag_pic ? INVALID_REGNUM \ 1157 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1158 : REAL_PIC_OFFSET_TABLE_REGNUM) 1159 1160 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1161 1162 /* This is overridden by <cygwin.h>. */ 1163 #define MS_AGGREGATE_RETURN 0 1164 1165 #define KEEP_AGGREGATE_RETURN_POINTER 0 1166 1167 /* Define the classes of registers for register constraints in the 1168 machine description. Also define ranges of constants. 1169 1170 One of the classes must always be named ALL_REGS and include all hard regs. 1171 If there is more than one class, another class must be named NO_REGS 1172 and contain no registers. 1173 1174 The name GENERAL_REGS must be the name of a class (or an alias for 1175 another name such as ALL_REGS). This is the class of registers 1176 that is allowed by "g" or "r" in a register constraint. 1177 Also, registers outside this class are allocated only when 1178 instructions express preferences for them. 1179 1180 The classes must be numbered in nondecreasing order; that is, 1181 a larger-numbered class must never be contained completely 1182 in a smaller-numbered class. 1183 1184 For any two classes, it is very desirable that there be another 1185 class that represents their union. 1186 1187 It might seem that class BREG is unnecessary, since no useful 386 1188 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1189 and the "b" register constraint is useful in asms for syscalls. 1190 1191 The flags, fpsr and fpcr registers are in no class. */ 1192 1193 enum reg_class 1194 { 1195 NO_REGS, 1196 AREG, DREG, CREG, BREG, SIREG, DIREG, 1197 AD_REGS, /* %eax/%edx for DImode */ 1198 CLOBBERED_REGS, /* call-clobbered integers */ 1199 Q_REGS, /* %eax %ebx %ecx %edx */ 1200 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1201 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1202 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1203 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp 1204 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ 1205 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1206 FLOAT_REGS, 1207 SSE_FIRST_REG, 1208 SSE_REGS, 1209 MMX_REGS, 1210 FP_TOP_SSE_REGS, 1211 FP_SECOND_SSE_REGS, 1212 FLOAT_SSE_REGS, 1213 FLOAT_INT_REGS, 1214 INT_SSE_REGS, 1215 FLOAT_INT_SSE_REGS, 1216 ALL_REGS, LIM_REG_CLASSES 1217 }; 1218 1219 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1220 1221 #define INTEGER_CLASS_P(CLASS) \ 1222 reg_class_subset_p ((CLASS), GENERAL_REGS) 1223 #define FLOAT_CLASS_P(CLASS) \ 1224 reg_class_subset_p ((CLASS), FLOAT_REGS) 1225 #define SSE_CLASS_P(CLASS) \ 1226 reg_class_subset_p ((CLASS), SSE_REGS) 1227 #define MMX_CLASS_P(CLASS) \ 1228 ((CLASS) == MMX_REGS) 1229 #define MAYBE_INTEGER_CLASS_P(CLASS) \ 1230 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1231 #define MAYBE_FLOAT_CLASS_P(CLASS) \ 1232 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1233 #define MAYBE_SSE_CLASS_P(CLASS) \ 1234 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1235 #define MAYBE_MMX_CLASS_P(CLASS) \ 1236 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1237 1238 #define Q_CLASS_P(CLASS) \ 1239 reg_class_subset_p ((CLASS), Q_REGS) 1240 1241 /* Give names of register classes as strings for dump file. */ 1242 1243 #define REG_CLASS_NAMES \ 1244 { "NO_REGS", \ 1245 "AREG", "DREG", "CREG", "BREG", \ 1246 "SIREG", "DIREG", \ 1247 "AD_REGS", \ 1248 "CLOBBERED_REGS", \ 1249 "Q_REGS", "NON_Q_REGS", \ 1250 "INDEX_REGS", \ 1251 "LEGACY_REGS", \ 1252 "GENERAL_REGS", \ 1253 "FP_TOP_REG", "FP_SECOND_REG", \ 1254 "FLOAT_REGS", \ 1255 "SSE_FIRST_REG", \ 1256 "SSE_REGS", \ 1257 "MMX_REGS", \ 1258 "FP_TOP_SSE_REGS", \ 1259 "FP_SECOND_SSE_REGS", \ 1260 "FLOAT_SSE_REGS", \ 1261 "FLOAT_INT_REGS", \ 1262 "INT_SSE_REGS", \ 1263 "FLOAT_INT_SSE_REGS", \ 1264 "ALL_REGS" } 1265 1266 /* Define which registers fit in which classes. This is an initializer 1267 for a vector of HARD_REG_SET of length N_REG_CLASSES. 1268 1269 Note that the default setting of CLOBBERED_REGS is for 32-bit; this 1270 is adjusted by TARGET_CONDITIONAL_REGISTER_USAGE for the 64-bit ABI 1271 in effect. */ 1272 1273 #define REG_CLASS_CONTENTS \ 1274 { { 0x00, 0x0 }, \ 1275 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1276 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1277 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1278 { 0x03, 0x0 }, /* AD_REGS */ \ 1279 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \ 1280 { 0x0f, 0x0 }, /* Q_REGS */ \ 1281 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1282 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1283 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1284 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1285 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1286 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1287 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ 1288 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1289 { 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1290 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1291 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1292 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1293 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1294 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1295 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1296 { 0xffffffff,0x1fffff } \ 1297 } 1298 1299 /* The same information, inverted: 1300 Return the class number of the smallest class containing 1301 reg number REGNO. This could be a conditional expression 1302 or could index an array. */ 1303 1304 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1305 1306 /* When this hook returns true for MODE, the compiler allows 1307 registers explicitly used in the rtl to be used as spill registers 1308 but prevents the compiler from extending the lifetime of these 1309 registers. */ 1310 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 1311 1312 #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG) 1313 1314 #define GENERAL_REGNO_P(N) \ 1315 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) 1316 1317 #define GENERAL_REG_P(X) \ 1318 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1319 1320 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1321 1322 #define REX_INT_REGNO_P(N) \ 1323 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 1324 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1325 1326 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1327 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1328 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1329 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1330 1331 #define X87_FLOAT_MODE_P(MODE) \ 1332 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 1333 1334 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1335 #define SSE_REGNO_P(N) \ 1336 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 1337 || REX_SSE_REGNO_P (N)) 1338 1339 #define REX_SSE_REGNO_P(N) \ 1340 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 1341 1342 #define SSE_REGNO(N) \ 1343 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1344 1345 #define SSE_FLOAT_MODE_P(MODE) \ 1346 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1347 1348 #define FMA4_VEC_FLOAT_MODE_P(MODE) \ 1349 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1350 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1351 1352 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1353 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1354 1355 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP))) 1356 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1357 1358 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1359 1360 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1361 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1362 1363 /* The class value for index registers, and the one for base regs. */ 1364 1365 #define INDEX_REG_CLASS INDEX_REGS 1366 #define BASE_REG_CLASS GENERAL_REGS 1367 1368 /* Place additional restrictions on the register class to use when it 1369 is necessary to be able to hold a value of mode MODE in a reload 1370 register for which class CLASS would ordinarily be used. */ 1371 1372 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1373 ((MODE) == QImode && !TARGET_64BIT \ 1374 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1375 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1376 ? Q_REGS : (CLASS)) 1377 1378 /* If we are copying between general and FP registers, we need a memory 1379 location. The same is true for SSE and MMX registers. */ 1380 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1381 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1382 1383 /* Get_secondary_mem widens integral modes to BITS_PER_WORD. 1384 There is no need to emit full 64 bit move on 64 bit targets 1385 for integral modes that can be moved using 32 bit move. */ 1386 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1387 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ 1388 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1389 : MODE) 1390 1391 /* Return a class of registers that cannot change FROM mode to TO mode. */ 1392 1393 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1394 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1395 1396 /* Stack layout; function entry, exit and calling. */ 1397 1398 /* Define this if pushing a word on the stack 1399 makes the stack pointer a smaller address. */ 1400 #define STACK_GROWS_DOWNWARD 1401 1402 /* Define this to nonzero if the nominal address of the stack frame 1403 is at the high-address end of the local variables; 1404 that is, each additional local variable allocated 1405 goes at a more negative offset in the frame. */ 1406 #define FRAME_GROWS_DOWNWARD 1 1407 1408 /* Offset within stack frame to start allocating local variables at. 1409 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1410 first local allocated. Otherwise, it is the offset to the BEGINNING 1411 of the first local allocated. */ 1412 #define STARTING_FRAME_OFFSET 0 1413 1414 /* If we generate an insn to push BYTES bytes, this says how many the stack 1415 pointer really advances by. On 386, we have pushw instruction that 1416 decrements by exactly 2 no matter what the position was, there is no pushb. 1417 1418 But as CIE data alignment factor on this arch is -4 for 32bit targets 1419 and -8 for 64bit targets, we need to make sure all stack pointer adjustments 1420 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */ 1421 1422 #define PUSH_ROUNDING(BYTES) \ 1423 (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD) 1424 1425 /* If defined, the maximum amount of space required for outgoing arguments 1426 will be computed and placed into the variable `crtl->outgoing_args_size'. 1427 No space will be pushed onto the stack for each call; instead, the 1428 function prologue should increase the stack frame size by this amount. 1429 1430 64-bit MS ABI seem to require 16 byte alignment everywhere except for 1431 function prologue and apilogue. This is not possible without 1432 ACCUMULATE_OUTGOING_ARGS. */ 1433 1434 #define ACCUMULATE_OUTGOING_ARGS \ 1435 (TARGET_ACCUMULATE_OUTGOING_ARGS || TARGET_64BIT_MS_ABI) 1436 1437 /* If defined, a C expression whose value is nonzero when we want to use PUSH 1438 instructions to pass outgoing arguments. */ 1439 1440 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1441 1442 /* We want the stack and args grow in opposite directions, even if 1443 PUSH_ARGS is 0. */ 1444 #define PUSH_ARGS_REVERSED 1 1445 1446 /* Offset of first parameter from the argument pointer register value. */ 1447 #define FIRST_PARM_OFFSET(FNDECL) 0 1448 1449 /* Define this macro if functions should assume that stack space has been 1450 allocated for arguments even when their values are passed in registers. 1451 1452 The value of this macro is the size, in bytes, of the area reserved for 1453 arguments passed in registers for the function represented by FNDECL. 1454 1455 This space can be allocated by the caller, or be a part of the 1456 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1457 which. */ 1458 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 1459 1460 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 1461 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) 1462 1463 /* Define how to find the value returned by a library function 1464 assuming the value has mode MODE. */ 1465 1466 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 1467 1468 /* Define the size of the result block used for communication between 1469 untyped_call and untyped_return. The block contains a DImode value 1470 followed by the block used by fnsave and frstor. */ 1471 1472 #define APPLY_RESULT_SIZE (8+108) 1473 1474 /* 1 if N is a possible register number for function argument passing. */ 1475 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1476 1477 #ifndef USED_FOR_TARGET 1478 /* Define a data type for recording info about an argument list 1479 during the scan of that argument list. This data type should 1480 hold all necessary information about the function itself 1481 and about the args processed so far, enough to enable macros 1482 such as FUNCTION_ARG to determine where the next arg should go. */ 1483 1484 typedef struct ix86_args { 1485 int words; /* # words passed so far */ 1486 int nregs; /* # registers available for passing */ 1487 int regno; /* next available register number */ 1488 int fastcall; /* fastcall or thiscall calling convention 1489 is used */ 1490 int sse_words; /* # sse words passed so far */ 1491 int sse_nregs; /* # sse registers available for passing */ 1492 int warn_avx; /* True when we want to warn about AVX ABI. */ 1493 int warn_sse; /* True when we want to warn about SSE ABI. */ 1494 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1495 int sse_regno; /* next available sse register number */ 1496 int mmx_words; /* # mmx words passed so far */ 1497 int mmx_nregs; /* # mmx registers available for passing */ 1498 int mmx_regno; /* next available mmx register number */ 1499 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1500 int caller; /* true if it is caller. */ 1501 int float_in_sse; /* Set to 1 or 2 for 32bit targets if 1502 SFmode/DFmode arguments should be passed 1503 in SSE registers. Otherwise 0. */ 1504 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1505 MS_ABI for ms abi. */ 1506 /* Nonzero if it passes 256bit AVX modes. */ 1507 BOOL_BITFIELD callee_pass_avx256_p : 1; 1508 /* Nonzero if it returns 256bit AVX modes. */ 1509 BOOL_BITFIELD callee_return_avx256_p : 1; 1510 } CUMULATIVE_ARGS; 1511 #endif 1512 1513 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1514 for a call to a function whose data type is FNTYPE. 1515 For a library call, FNTYPE is 0. */ 1516 1517 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1518 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 1519 (N_NAMED_ARGS) != -1) 1520 1521 /* Output assembler code to FILE to increment profiler label # LABELNO 1522 for profiling a function entry. */ 1523 1524 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1525 1526 #define MCOUNT_NAME "_mcount" 1527 1528 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" 1529 1530 #define PROFILE_COUNT_REGISTER "edx" 1531 1532 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1533 the stack pointer does not matter. The value is tested only in 1534 functions that have frame pointers. 1535 No definition is equivalent to always zero. */ 1536 /* Note on the 386 it might be more efficient not to define this since 1537 we have to restore it ourselves from the frame pointer, in order to 1538 use pop */ 1539 1540 #define EXIT_IGNORE_STACK 1 1541 1542 /* Output assembler code for a block containing the constant parts 1543 of a trampoline, leaving space for the variable parts. */ 1544 1545 /* On the 386, the trampoline contains two instructions: 1546 mov #STATIC,ecx 1547 jmp FUNCTION 1548 The trampoline is generated entirely at runtime. The operand of JMP 1549 is the address of FUNCTION relative to the instruction following the 1550 JMP (which is 5 bytes long). */ 1551 1552 /* Length in units of the trampoline for entering a nested function. */ 1553 1554 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) 1555 1556 /* Definitions for register eliminations. 1557 1558 This is an array of structures. Each structure initializes one pair 1559 of eliminable registers. The "from" register number is given first, 1560 followed by "to". Eliminations of the same "from" register are listed 1561 in order of preference. 1562 1563 There are two registers that can always be eliminated on the i386. 1564 The frame pointer and the arg pointer can be replaced by either the 1565 hard frame pointer or to the stack pointer, depending upon the 1566 circumstances. The hard frame pointer is not used before reload and 1567 so it is not eligible for elimination. */ 1568 1569 #define ELIMINABLE_REGS \ 1570 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1571 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1572 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1573 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1574 1575 /* Define the offset between two registers, one to be eliminated, and the other 1576 its replacement, at the start of a routine. */ 1577 1578 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1579 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1580 1581 /* Addressing modes, and classification of registers for them. */ 1582 1583 /* Macros to check register numbers against specific register classes. */ 1584 1585 /* These assume that REGNO is a hard or pseudo reg number. 1586 They give nonzero only if REGNO is a hard reg of the suitable class 1587 or a pseudo reg currently allocated to a suitable hard reg. 1588 Since they use reg_renumber, they are safe only once reg_renumber 1589 has been allocated, which happens in local-alloc.c. */ 1590 1591 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1592 ((REGNO) < STACK_POINTER_REGNUM \ 1593 || REX_INT_REGNO_P (REGNO) \ 1594 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 1595 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1596 1597 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1598 (GENERAL_REGNO_P (REGNO) \ 1599 || (REGNO) == ARG_POINTER_REGNUM \ 1600 || (REGNO) == FRAME_POINTER_REGNUM \ 1601 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1602 1603 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1604 and check its validity for a certain class. 1605 We have two alternate definitions for each of them. 1606 The usual definition accepts all pseudo regs; the other rejects 1607 them unless they have been allocated suitable hard regs. 1608 The symbol REG_OK_STRICT causes the latter definition to be used. 1609 1610 Most source files want to accept pseudo regs in the hope that 1611 they will get allocated to the class that the insn wants them to be in. 1612 Source files for reload pass need to be strict. 1613 After reload, it makes no difference, since pseudo regs have 1614 been eliminated by then. */ 1615 1616 1617 /* Non strict versions, pseudos are ok. */ 1618 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1619 (REGNO (X) < STACK_POINTER_REGNUM \ 1620 || REX_INT_REGNO_P (REGNO (X)) \ 1621 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1622 1623 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1624 (GENERAL_REGNO_P (REGNO (X)) \ 1625 || REGNO (X) == ARG_POINTER_REGNUM \ 1626 || REGNO (X) == FRAME_POINTER_REGNUM \ 1627 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1628 1629 /* Strict versions, hard registers only */ 1630 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1631 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1632 1633 #ifndef REG_OK_STRICT 1634 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1635 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1636 1637 #else 1638 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1639 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1640 #endif 1641 1642 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1643 that is a valid memory address for an instruction. 1644 The MODE argument is the machine mode for the MEM expression 1645 that wants to use this address. 1646 1647 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 1648 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1649 1650 See legitimize_pic_address in i386.c for details as to what 1651 constitutes a legitimate address when -fpic is used. */ 1652 1653 #define MAX_REGS_PER_ADDRESS 2 1654 1655 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1656 1657 /* Try a machine-dependent way of reloading an illegitimate address 1658 operand. If we find one, push the reload and jump to WIN. This 1659 macro is used in only one place: `find_reloads_address' in reload.c. */ 1660 1661 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \ 1662 do { \ 1663 if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1664 (int)(TYPE), (INDL))) \ 1665 goto WIN; \ 1666 } while (0) 1667 1668 /* If defined, a C expression to determine the base term of address X. 1669 This macro is used in only one place: `find_base_term' in alias.c. 1670 1671 It is always safe for this macro to not be defined. It exists so 1672 that alias analysis can understand machine-dependent addresses. 1673 1674 The typical use of this macro is to handle addresses containing 1675 a label_ref or symbol_ref within an UNSPEC. */ 1676 1677 #define FIND_BASE_TERM(X) ix86_find_base_term (X) 1678 1679 /* Nonzero if the constant value X is a legitimate general operand 1680 when generating PIC code. It is given that flag_pic is on and 1681 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1682 1683 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1684 1685 #define SYMBOLIC_CONST(X) \ 1686 (GET_CODE (X) == SYMBOL_REF \ 1687 || GET_CODE (X) == LABEL_REF \ 1688 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1689 1690 /* Max number of args passed in registers. If this is more than 3, we will 1691 have problems with ebx (register #4), since it is a caller save register and 1692 is also used as the pic register in ELF. So for now, don't allow more than 1693 3 registers to be passed in registers. */ 1694 1695 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 1696 #define X86_64_REGPARM_MAX 6 1697 #define X86_64_MS_REGPARM_MAX 4 1698 1699 #define X86_32_REGPARM_MAX 3 1700 1701 #define REGPARM_MAX \ 1702 (TARGET_64BIT \ 1703 ? (TARGET_64BIT_MS_ABI \ 1704 ? X86_64_MS_REGPARM_MAX \ 1705 : X86_64_REGPARM_MAX) \ 1706 : X86_32_REGPARM_MAX) 1707 1708 #define X86_64_SSE_REGPARM_MAX 8 1709 #define X86_64_MS_SSE_REGPARM_MAX 4 1710 1711 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 1712 1713 #define SSE_REGPARM_MAX \ 1714 (TARGET_64BIT \ 1715 ? (TARGET_64BIT_MS_ABI \ 1716 ? X86_64_MS_SSE_REGPARM_MAX \ 1717 : X86_64_SSE_REGPARM_MAX) \ 1718 : X86_32_SSE_REGPARM_MAX) 1719 1720 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1721 1722 /* Specify the machine mode that this machine uses 1723 for the index in the tablejump instruction. */ 1724 #define CASE_VECTOR_MODE \ 1725 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 1726 1727 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1728 #define DEFAULT_SIGNED_CHAR 1 1729 1730 /* Max number of bytes we can move from memory to memory 1731 in one reasonably fast instruction. */ 1732 #define MOVE_MAX 16 1733 1734 /* MOVE_MAX_PIECES is the number of bytes at a time which we can 1735 move efficiently, as opposed to MOVE_MAX which is the maximum 1736 number of bytes we can move with a single instruction. */ 1737 #define MOVE_MAX_PIECES UNITS_PER_WORD 1738 1739 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1740 move-instruction pairs, we will do a movmem or libcall instead. 1741 Increasing the value will always make code faster, but eventually 1742 incurs high cost in increased code size. 1743 1744 If you don't define this, a reasonable default is used. */ 1745 1746 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 1747 1748 /* If a clear memory operation would take CLEAR_RATIO or more simple 1749 move-instruction sequences, we will do a clrmem or libcall instead. */ 1750 1751 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) 1752 1753 /* Define if shifts truncate the shift count which implies one can 1754 omit a sign-extension or zero-extension of a shift count. 1755 1756 On i386, shifts do truncate the count. But bit test instructions 1757 take the modulo of the bit offset operand. */ 1758 1759 /* #define SHIFT_COUNT_TRUNCATED */ 1760 1761 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1762 is done just by pretending it is already truncated. */ 1763 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1764 1765 /* A macro to update M and UNSIGNEDP when an object whose type is 1766 TYPE and which has the specified mode and signedness is to be 1767 stored in a register. This macro is only called when TYPE is a 1768 scalar type. 1769 1770 On i386 it is sometimes useful to promote HImode and QImode 1771 quantities to SImode. The choice depends on target type. */ 1772 1773 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1774 do { \ 1775 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1776 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1777 (MODE) = SImode; \ 1778 } while (0) 1779 1780 /* Specify the machine mode that pointers have. 1781 After generation of rtl, the compiler makes no further distinction 1782 between pointers and any other objects of this machine mode. */ 1783 #define Pmode (TARGET_64BIT ? DImode : SImode) 1784 1785 /* A C expression whose value is zero if pointers that need to be extended 1786 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1787 greater then zero if they are zero-extended and less then zero if the 1788 ptr_extend instruction should be used. */ 1789 1790 #define POINTERS_EXTEND_UNSIGNED 1 1791 1792 /* A function address in a call instruction 1793 is a byte address (for indexing purposes) 1794 so give the MEM rtx a byte's mode. */ 1795 #define FUNCTION_MODE QImode 1796 1797 1798 /* A C expression for the cost of a branch instruction. A value of 1 1799 is the default; other values are interpreted relative to that. */ 1800 1801 #define BRANCH_COST(speed_p, predictable_p) \ 1802 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 1803 1804 /* Define this macro as a C expression which is nonzero if accessing 1805 less than a word of memory (i.e. a `char' or a `short') is no 1806 faster than accessing a word of memory, i.e., if such access 1807 require more than one instruction or if there is no difference in 1808 cost between byte and (aligned) word loads. 1809 1810 When this macro is not defined, the compiler will access a field by 1811 finding the smallest containing object; when it is defined, a 1812 fullword load will be used if alignment permits. Unless bytes 1813 accesses are faster than word accesses, using word accesses is 1814 preferable since it may eliminate subsequent memory access if 1815 subsequent accesses occur to other fields in the same word of the 1816 structure, but to different bytes. */ 1817 1818 #define SLOW_BYTE_ACCESS 0 1819 1820 /* Nonzero if access to memory by shorts is slow and undesirable. */ 1821 #define SLOW_SHORT_ACCESS 0 1822 1823 /* Define this macro to be the value 1 if unaligned accesses have a 1824 cost many times greater than aligned accesses, for example if they 1825 are emulated in a trap handler. 1826 1827 When this macro is nonzero, the compiler will act as if 1828 `STRICT_ALIGNMENT' were nonzero when generating code for block 1829 moves. This can cause significantly more instructions to be 1830 produced. Therefore, do not set this macro nonzero if unaligned 1831 accesses only add a cycle or two to the time for a memory access. 1832 1833 If the value of this macro is always zero, it need not be defined. */ 1834 1835 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1836 1837 /* Define this macro if it is as good or better to call a constant 1838 function address than to call an address kept in a register. 1839 1840 Desirable on the 386 because a CALL with a constant address is 1841 faster than one with a register address. */ 1842 1843 #define NO_FUNCTION_CSE 1844 1845 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1846 return the mode to be used for the comparison. 1847 1848 For floating-point equality comparisons, CCFPEQmode should be used. 1849 VOIDmode should be used in all other cases. 1850 1851 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1852 possible, to allow for more combinations. */ 1853 1854 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1855 1856 /* Return nonzero if MODE implies a floating point inequality can be 1857 reversed. */ 1858 1859 #define REVERSIBLE_CC_MODE(MODE) 1 1860 1861 /* A C expression whose value is reversed condition code of the CODE for 1862 comparison done in CC_MODE mode. */ 1863 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 1864 1865 1866 /* Control the assembler format that we output, to the extent 1867 this does not vary between assemblers. */ 1868 1869 /* How to refer to registers in assembler output. 1870 This sequence is indexed by compiler's hard-register-number (see above). */ 1871 1872 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 1873 For non floating point regs, the following are the HImode names. 1874 1875 For float regs, the stack top is sometimes referred to as "%st(0)" 1876 instead of just "%st". TARGET_PRINT_OPERAND handles this with the 1877 "y" code. */ 1878 1879 #define HI_REGISTER_NAMES \ 1880 {"ax","dx","cx","bx","si","di","bp","sp", \ 1881 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 1882 "argp", "flags", "fpsr", "fpcr", "frame", \ 1883 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 1884 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 1885 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1886 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 1887 1888 #define REGISTER_NAMES HI_REGISTER_NAMES 1889 1890 /* Table of additional register names to use in user input. */ 1891 1892 #define ADDITIONAL_REGISTER_NAMES \ 1893 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 1894 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 1895 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 1896 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 1897 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 1898 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 1899 1900 /* Note we are omitting these since currently I don't know how 1901 to get gcc to use these, since they want the same but different 1902 number as al, and ax. 1903 */ 1904 1905 #define QI_REGISTER_NAMES \ 1906 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 1907 1908 /* These parallel the array above, and can be used to access bits 8:15 1909 of regs 0 through 3. */ 1910 1911 #define QI_HIGH_REGISTER_NAMES \ 1912 {"ah", "dh", "ch", "bh", } 1913 1914 /* How to renumber registers for dbx and gdb. */ 1915 1916 #define DBX_REGISTER_NUMBER(N) \ 1917 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 1918 1919 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 1920 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 1921 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 1922 1923 /* Before the prologue, RA is at 0(%esp). */ 1924 #define INCOMING_RETURN_ADDR_RTX \ 1925 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 1926 1927 /* After the prologue, RA is at -4(AP) in the current frame. */ 1928 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1929 ((COUNT) == 0 \ 1930 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 1931 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 1932 1933 /* PC is dbx register 8; let's use that column for RA. */ 1934 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 1935 1936 /* Before the prologue, the top of the frame is at 4(%esp). */ 1937 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 1938 1939 /* Describe how we implement __builtin_eh_return. */ 1940 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) 1941 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) 1942 1943 1944 /* Select a format to encode pointers in exception handling data. CODE 1945 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1946 true if the symbol may be affected by dynamic relocations. 1947 1948 ??? All x86 object file formats are capable of representing this. 1949 After all, the relocation needed is the same as for the call insn. 1950 Whether or not a particular assembler allows us to enter such, I 1951 guess we'll have to see. */ 1952 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1953 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 1954 1955 /* This is how to output an insn to push a register on the stack. 1956 It need not be very fast code. */ 1957 1958 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 1959 do { \ 1960 if (TARGET_64BIT) \ 1961 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 1962 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 1963 else \ 1964 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 1965 } while (0) 1966 1967 /* This is how to output an insn to pop a register from the stack. 1968 It need not be very fast code. */ 1969 1970 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 1971 do { \ 1972 if (TARGET_64BIT) \ 1973 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 1974 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 1975 else \ 1976 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 1977 } while (0) 1978 1979 /* This is how to output an element of a case-vector that is absolute. */ 1980 1981 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1982 ix86_output_addr_vec_elt ((FILE), (VALUE)) 1983 1984 /* This is how to output an element of a case-vector that is relative. */ 1985 1986 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1987 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 1988 1989 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ 1990 1991 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 1992 { \ 1993 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 1994 (PTR) += TARGET_AVX ? 1 : 2; \ 1995 } 1996 1997 /* A C statement or statements which output an assembler instruction 1998 opcode to the stdio stream STREAM. The macro-operand PTR is a 1999 variable of type `char *' which points to the opcode name in 2000 its "internal" form--the form that is written in the machine 2001 description. */ 2002 2003 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2004 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 2005 2006 /* A C statement to output to the stdio stream FILE an assembler 2007 command to pad the location counter to a multiple of 1<<LOG 2008 bytes if it is within MAX_SKIP bytes. */ 2009 2010 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2011 #undef ASM_OUTPUT_MAX_SKIP_PAD 2012 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2013 if ((LOG) != 0) \ 2014 { \ 2015 if ((MAX_SKIP) == 0) \ 2016 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2017 else \ 2018 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2019 } 2020 #endif 2021 2022 /* Write the extra assembler code needed to declare a function 2023 properly. */ 2024 2025 #undef ASM_OUTPUT_FUNCTION_LABEL 2026 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 2027 ix86_asm_output_function_label (FILE, NAME, DECL) 2028 2029 /* Under some conditions we need jump tables in the text section, 2030 because the assembler cannot handle label differences between 2031 sections. This is the case for x86_64 on Mach-O for example. */ 2032 2033 #define JUMP_TABLES_IN_TEXT_SECTION \ 2034 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2035 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2036 2037 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2038 and switch back. For x86 we do this only to save a few bytes that 2039 would otherwise be unused in the text section. */ 2040 #define CRT_MKSTR2(VAL) #VAL 2041 #define CRT_MKSTR(x) CRT_MKSTR2(x) 2042 2043 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2044 asm (SECTION_OP "\n\t" \ 2045 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 2046 TEXT_SECTION_ASM_OP); 2047 2048 /* Which processor to tune code generation for. */ 2049 2050 enum processor_type 2051 { 2052 PROCESSOR_I386 = 0, /* 80386 */ 2053 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2054 PROCESSOR_PENTIUM, 2055 PROCESSOR_PENTIUMPRO, 2056 PROCESSOR_GEODE, 2057 PROCESSOR_K6, 2058 PROCESSOR_ATHLON, 2059 PROCESSOR_PENTIUM4, 2060 PROCESSOR_K8, 2061 PROCESSOR_NOCONA, 2062 PROCESSOR_CORE2_32, 2063 PROCESSOR_CORE2_64, 2064 PROCESSOR_COREI7_32, 2065 PROCESSOR_COREI7_64, 2066 PROCESSOR_GENERIC32, 2067 PROCESSOR_GENERIC64, 2068 PROCESSOR_AMDFAM10, 2069 PROCESSOR_BDVER1, 2070 PROCESSOR_BDVER2, 2071 PROCESSOR_BTVER1, 2072 PROCESSOR_ATOM, 2073 PROCESSOR_max 2074 }; 2075 2076 extern enum processor_type ix86_tune; 2077 extern enum processor_type ix86_arch; 2078 2079 /* Size of the RED_ZONE area. */ 2080 #define RED_ZONE_SIZE 128 2081 /* Reserved area of the red zone for temporaries. */ 2082 #define RED_ZONE_RESERVE 8 2083 2084 extern unsigned int ix86_preferred_stack_boundary; 2085 extern unsigned int ix86_incoming_stack_boundary; 2086 2087 /* Smallest class containing REGNO. */ 2088 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2089 2090 enum ix86_fpcmp_strategy { 2091 IX86_FPCMP_SAHF, 2092 IX86_FPCMP_COMI, 2093 IX86_FPCMP_ARITH 2094 }; 2095 2096 /* To properly truncate FP values into integers, we need to set i387 control 2097 word. We can't emit proper mode switching code before reload, as spills 2098 generated by reload may truncate values incorrectly, but we still can avoid 2099 redundant computation of new control word by the mode switching pass. 2100 The fldcw instructions are still emitted redundantly, but this is probably 2101 not going to be noticeable problem, as most CPUs do have fast path for 2102 the sequence. 2103 2104 The machinery is to emit simple truncation instructions and split them 2105 before reload to instructions having USEs of two memory locations that 2106 are filled by this code to old and new control word. 2107 2108 Post-reload pass may be later used to eliminate the redundant fildcw if 2109 needed. */ 2110 2111 enum ix86_entity 2112 { 2113 I387_TRUNC = 0, 2114 I387_FLOOR, 2115 I387_CEIL, 2116 I387_MASK_PM, 2117 MAX_386_ENTITIES 2118 }; 2119 2120 enum ix86_stack_slot 2121 { 2122 SLOT_TEMP = 0, 2123 SLOT_CW_STORED, 2124 SLOT_CW_TRUNC, 2125 SLOT_CW_FLOOR, 2126 SLOT_CW_CEIL, 2127 SLOT_CW_MASK_PM, 2128 MAX_386_STACK_LOCALS 2129 }; 2130 2131 /* Define this macro if the port needs extra instructions inserted 2132 for mode switching in an optimizing compilation. */ 2133 2134 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2135 ix86_optimize_mode_switching[(ENTITY)] 2136 2137 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2138 initializer for an array of integers. Each initializer element N 2139 refers to an entity that needs mode switching, and specifies the 2140 number of different modes that might need to be set for this 2141 entity. The position of the initializer in the initializer - 2142 starting counting at zero - determines the integer that is used to 2143 refer to the mode-switched entity in question. */ 2144 2145 #define NUM_MODES_FOR_MODE_SWITCHING \ 2146 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2147 2148 /* ENTITY is an integer specifying a mode-switched entity. If 2149 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2150 return an integer value not larger than the corresponding element 2151 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2152 must be switched into prior to the execution of INSN. */ 2153 2154 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2155 2156 /* This macro specifies the order in which modes for ENTITY are 2157 processed. 0 is the highest priority. */ 2158 2159 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2160 2161 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2162 is the set of hard registers live at the point where the insn(s) 2163 are to be inserted. */ 2164 2165 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2166 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ 2167 ? emit_i387_cw_initialization (MODE), 0 \ 2168 : 0) 2169 2170 2171 /* Avoid renaming of stack registers, as doing so in combination with 2172 scheduling just increases amount of live registers at time and in 2173 the turn amount of fxch instructions needed. 2174 2175 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2176 2177 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2178 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG)) 2179 2180 2181 #define FASTCALL_PREFIX '@' 2182 2183 /* Machine specific frame tracking during prologue/epilogue generation. */ 2184 2185 #ifndef USED_FOR_TARGET 2186 struct GTY(()) machine_frame_state 2187 { 2188 /* This pair tracks the currently active CFA as reg+offset. When reg 2189 is drap_reg, we don't bother trying to record here the real CFA when 2190 it might really be a DW_CFA_def_cfa_expression. */ 2191 rtx cfa_reg; 2192 HOST_WIDE_INT cfa_offset; 2193 2194 /* The current offset (canonically from the CFA) of ESP and EBP. 2195 When stack frame re-alignment is active, these may not be relative 2196 to the CFA. However, in all cases they are relative to the offsets 2197 of the saved registers stored in ix86_frame. */ 2198 HOST_WIDE_INT sp_offset; 2199 HOST_WIDE_INT fp_offset; 2200 2201 /* The size of the red-zone that may be assumed for the purposes of 2202 eliding register restore notes in the epilogue. This may be zero 2203 if no red-zone is in effect, or may be reduced from the real 2204 red-zone value by a maximum runtime stack re-alignment value. */ 2205 int red_zone_offset; 2206 2207 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid 2208 value within the frame. If false then the offset above should be 2209 ignored. Note that DRAP, if valid, *always* points to the CFA and 2210 thus has an offset of zero. */ 2211 BOOL_BITFIELD sp_valid : 1; 2212 BOOL_BITFIELD fp_valid : 1; 2213 BOOL_BITFIELD drap_valid : 1; 2214 2215 /* Indicate whether the local stack frame has been re-aligned. When 2216 set, the SP/FP offsets above are relative to the aligned frame 2217 and not the CFA. */ 2218 BOOL_BITFIELD realigned : 1; 2219 }; 2220 2221 /* Private to winnt.c. */ 2222 struct seh_frame_state; 2223 2224 struct GTY(()) machine_function { 2225 struct stack_local_entry *stack_locals; 2226 const char *some_ld_name; 2227 int varargs_gpr_size; 2228 int varargs_fpr_size; 2229 int optimize_mode_switching[MAX_386_ENTITIES]; 2230 2231 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE 2232 has been computed for. */ 2233 int use_fast_prologue_epilogue_nregs; 2234 2235 /* For -fsplit-stack support: A stack local which holds a pointer to 2236 the stack arguments for a function with a variable number of 2237 arguments. This is set at the start of the function and is used 2238 to initialize the overflow_arg_area field of the va_list 2239 structure. */ 2240 rtx split_stack_varargs_pointer; 2241 2242 /* This value is used for amd64 targets and specifies the current abi 2243 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 2244 ENUM_BITFIELD(calling_abi) call_abi : 8; 2245 2246 /* Nonzero if the function accesses a previous frame. */ 2247 BOOL_BITFIELD accesses_prev_frame : 1; 2248 2249 /* Nonzero if the function requires a CLD in the prologue. */ 2250 BOOL_BITFIELD needs_cld : 1; 2251 2252 /* Set by ix86_compute_frame_layout and used by prologue/epilogue 2253 expander to determine the style used. */ 2254 BOOL_BITFIELD use_fast_prologue_epilogue : 1; 2255 2256 /* If true, the current function needs the default PIC register, not 2257 an alternate register (on x86) and must not use the red zone (on 2258 x86_64), even if it's a leaf function. We don't want the 2259 function to be regarded as non-leaf because TLS calls need not 2260 affect register allocation. This flag is set when a TLS call 2261 instruction is expanded within a function, and never reset, even 2262 if all such instructions are optimized away. Use the 2263 ix86_current_function_calls_tls_descriptor macro for a better 2264 approximation. */ 2265 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 2266 2267 /* If true, the current function has a STATIC_CHAIN is placed on the 2268 stack below the return address. */ 2269 BOOL_BITFIELD static_chain_on_stack : 1; 2270 2271 /* Nonzero if caller passes 256bit AVX modes. */ 2272 BOOL_BITFIELD caller_pass_avx256_p : 1; 2273 2274 /* Nonzero if caller returns 256bit AVX modes. */ 2275 BOOL_BITFIELD caller_return_avx256_p : 1; 2276 2277 /* Nonzero if the current callee passes 256bit AVX modes. */ 2278 BOOL_BITFIELD callee_pass_avx256_p : 1; 2279 2280 /* Nonzero if the current callee returns 256bit AVX modes. */ 2281 BOOL_BITFIELD callee_return_avx256_p : 1; 2282 2283 /* Nonzero if rescan vzerouppers in the current function is needed. */ 2284 BOOL_BITFIELD rescan_vzeroupper_p : 1; 2285 2286 /* During prologue/epilogue generation, the current frame state. 2287 Otherwise, the frame state at the end of the prologue. */ 2288 struct machine_frame_state fs; 2289 2290 /* During SEH output, this is non-null. */ 2291 struct seh_frame_state * GTY((skip(""))) seh; 2292 }; 2293 #endif 2294 2295 #define ix86_stack_locals (cfun->machine->stack_locals) 2296 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 2297 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 2298 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2299 #define ix86_current_function_needs_cld (cfun->machine->needs_cld) 2300 #define ix86_tls_descriptor_calls_expanded_in_cfun \ 2301 (cfun->machine->tls_descriptor_call_expanded_p) 2302 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2303 calls are optimized away, we try to detect cases in which it was 2304 optimized away. Since such instructions (use (reg REG_SP)), we can 2305 verify whether there's any such instruction live by testing that 2306 REG_SP is live. */ 2307 #define ix86_current_function_calls_tls_descriptor \ 2308 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 2309 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 2310 2311 /* Control behavior of x86_file_start. */ 2312 #define X86_FILE_START_VERSION_DIRECTIVE false 2313 #define X86_FILE_START_FLTUSED false 2314 2315 /* Flag to mark data that is in the large address area. */ 2316 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2317 #define SYMBOL_REF_FAR_ADDR_P(X) \ 2318 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2319 2320 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 2321 have defined always, to avoid ifdefing. */ 2322 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 2323 #define SYMBOL_REF_DLLIMPORT_P(X) \ 2324 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 2325 2326 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 2327 #define SYMBOL_REF_DLLEXPORT_P(X) \ 2328 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 2329 2330 extern void debug_ready_dispatch (void); 2331 extern void debug_dispatch_window (int); 2332 2333 /* The value at zero is only defined for the BMI instructions 2334 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ 2335 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2336 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI) 2337 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2338 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT) 2339 2340 2341 /* Flags returned by ix86_get_callcvt (). */ 2342 #define IX86_CALLCVT_CDECL 0x1 2343 #define IX86_CALLCVT_STDCALL 0x2 2344 #define IX86_CALLCVT_FASTCALL 0x4 2345 #define IX86_CALLCVT_THISCALL 0x8 2346 #define IX86_CALLCVT_REGPARM 0x10 2347 #define IX86_CALLCVT_SSEREGPARM 0x20 2348 2349 #define IX86_BASE_CALLCVT(FLAGS) \ 2350 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ 2351 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) 2352 2353 #define RECIP_MASK_NONE 0x00 2354 #define RECIP_MASK_DIV 0x01 2355 #define RECIP_MASK_SQRT 0x02 2356 #define RECIP_MASK_VEC_DIV 0x04 2357 #define RECIP_MASK_VEC_SQRT 0x08 2358 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ 2359 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2360 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2361 2362 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) 2363 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) 2364 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) 2365 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) 2366 2367 /* 2368 Local variables: 2369 version-control: t 2370 End: 2371 */ 2372