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Searched refs:TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h15533 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00 macro
H A Dgfx_8_1_sh_mask.h16103 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h8987 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK … macro
H A Dgc_9_1_sh_mask.h10613 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK … macro
H A Dgc_9_2_1_sh_mask.h10443 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK … macro