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Searched refs:TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h10664 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L macro
H A Dgfx_7_2_sh_mask.h13705 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 macro
H A Dgfx_8_0_sh_mask.h15627 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 macro
H A Dgfx_8_1_sh_mask.h16197 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h21960 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … macro
H A Dgc_9_1_sh_mask.h23396 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … macro
H A Dgc_9_2_1_sh_mask.h23391 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK … macro