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Searched refs:TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h10674 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L macro
H A Dgfx_7_2_sh_mask.h13687 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 macro
H A Dgfx_8_0_sh_mask.h15609 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 macro
H A Dgfx_8_1_sh_mask.h16179 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h21951 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK … macro
H A Dgc_9_1_sh_mask.h23387 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK … macro
H A Dgc_9_2_1_sh_mask.h23382 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK … macro