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Searched refs:TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h10700 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL macro
H A Dgfx_7_2_sh_mask.h13689 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff macro
H A Dgfx_8_0_sh_mask.h15611 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff macro
H A Dgfx_8_1_sh_mask.h16181 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h21967 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK … macro
H A Dgc_9_1_sh_mask.h23403 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK … macro
H A Dgc_9_2_1_sh_mask.h23398 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK … macro