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Searched refs:TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h14346 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 macro
H A Dgfx_8_0_sh_mask.h16246 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 macro
H A Dgfx_8_1_sh_mask.h16826 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h8823 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT … macro
H A Dgc_9_1_sh_mask.h10449 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h10279 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT … macro