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Searched refs:TDC_MV_AVERAGE__IDD__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h2414 #define TDC_MV_AVERAGE__IDD__SHIFT 0x0 macro
H A Dsmu_7_1_1_sh_mask.h2770 #define TDC_MV_AVERAGE__IDD__SHIFT 0x0 macro
H A Dsmu_7_0_1_sh_mask.h2612 #define TDC_MV_AVERAGE__IDD__SHIFT 0x0 macro
H A Dsmu_7_1_0_sh_mask.h2610 #define TDC_MV_AVERAGE__IDD__SHIFT 0x0 macro
H A Dsmu_7_1_2_sh_mask.h898 #define TDC_MV_AVERAGE__IDD__SHIFT 0x0 macro
H A Dsmu_7_1_3_sh_mask.h926 #define TDC_MV_AVERAGE__IDD__SHIFT 0x0 macro