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Searched refs:UVD_VCPU_CACHE_OFFSET0 (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Duvd_v4_2.c52 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v4_2_resume()
H A Duvd_v2_2.c115 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v2_2_resume()
H A Duvd_v1_0.c123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v1_0_resume()
H A Drv770d.h1002 #define UVD_VCPU_CACHE_OFFSET0 0xf4d8 macro
H A Dcikd.h2075 #define UVD_VCPU_CACHE_OFFSET0 0xf608 macro
H A Dr600d.h1515 #define UVD_VCPU_CACHE_OFFSET0 0xf608 macro