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Searched refs:UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h658 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT … macro
H A Duvd_4_0_sh_mask.h753 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x00000000 macro
H A Duvd_4_2_sh_mask.h532 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Duvd_5_0_sh_mask.h564 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h566 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1132 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT … macro