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Searched refs:VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h11225 #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x0000001f macro
H A Dgfx_7_2_sh_mask.h17250 #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f macro
H A Dgfx_8_0_sh_mask.h19560 #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f macro
H A Dgfx_8_1_sh_mask.h20162 #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f macro