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Searched refs:VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h11644 #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x03ffffffL macro
H A Dgfx_7_2_sh_mask.h17595 #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff macro
H A Dgfx_8_0_sh_mask.h19905 #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff macro
H A Dgfx_8_1_sh_mask.h20507 #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff macro