Home
last modified time | relevance | path

Searched refs:VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h11770 #define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x00000020L macro
H A Dgfx_7_2_sh_mask.h17679 #define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 macro
H A Dgfx_8_0_sh_mask.h19989 #define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 macro
H A Dgfx_8_1_sh_mask.h20591 #define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 macro