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Searched refs:VGT_DEBUG_REG33__tess_type_p0_q__SHIFT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h12123 #define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x00000018 macro
H A Dgfx_7_2_sh_mask.h18012 #define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 macro
H A Dgfx_8_0_sh_mask.h20270 #define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 macro
H A Dgfx_8_1_sh_mask.h20872 #define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 macro