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Searched refs:VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h12145 #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 macro
H A Dgfx_7_2_sh_mask.h18060 #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 macro
H A Dgfx_8_0_sh_mask.h20318 #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 macro
H A Dgfx_8_1_sh_mask.h20920 #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 macro