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Searched refs:VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h17939 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000 macro
H A Dgfx_8_1_sh_mask.h18529 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h17436 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
H A Dgc_9_1_sh_mask.h18872 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
H A Dgc_9_2_1_sh_mask.h18763 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro