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Searched refs:VISLANDS30_IV_SRCID_VCE_TRAP (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/ivsrcid/
H A Divsrcid_vislands30.h227 #define VISLANDS30_IV_SRCID_VCE_TRAP 0x000000a7 /* 167 */ macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v3_0.c426 …r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.ir… in vce_v3_0_sw_init()