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Searched refs:VLINE_ACK (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dsid.h806 # define VLINE_ACK (1 << 4) macro
H A Dcik.c7302 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7306 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7318 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7322 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7335 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7339 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
H A Dcikd.h877 # define VLINE_ACK (1 << 4) macro
H A Devergreend.h1271 # define VLINE_ACK (1 << 4) macro
H A Devergreen.c4621 VLINE_ACK); in evergreen_irq_ack()
H A Dsi.c6160 VLINE_ACK); in si_irq_ack()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c3186 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); in dce_v10_0_crtc_vline_int_ack()
H A Ddce_v11_0.c3312 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); in dce_v11_0_crtc_vline_int_ack()