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Searched refs:WREG32_AND (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dr600_hdmi.c382 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset, in r600_set_audio_packet()
410 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); in r600_set_mute()
465 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_hdmi_update_audio_settings()
500 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); in r600_hdmi_enable()
508 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); in r600_hdmi_enable()
516 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); in r600_hdmi_enable()
H A Devergreen_hdmi.c420 WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE); in dce4_set_mute()
449 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
453 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
509 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_dp_enable()
H A Ddce3_1_afmt.c243 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); in dce3_2_set_mute()
H A Devergreen.c1730 WREG32_AND(DC_HPDx_INT_CONTROL(hpd), ~DC_HPDx_INT_POLARITY); in evergreen_hpd_set_polarity()
4468 WREG32_AND(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_POLARITY); in evergreen_disable_interrupt_state()
H A Dradeon.h2573 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) macro
H A Dsi.c5959 WREG32_AND(DC_HPDx_INT_CONTROL(i), in si_disable_interrupt_state()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu.h1654 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) macro