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Searched refs:WREG32_ENDPOINT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Ddce6_afmt.c157 WREG32_ENDPOINT(dig->pin->offset, in dce6_afmt_write_latency_fields()
184 WREG32_ENDPOINT(dig->pin->offset, in dce6_afmt_hdmi_write_speaker_allocation()
211 WREG32_ENDPOINT(dig->pin->offset, in dce6_afmt_dp_write_speaker_allocation()
266 WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value); in dce6_afmt_write_sad_regs()
277 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce6_audio_enable()
H A Ddce3_1_afmt.c47 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce3_2_afmt_hdmi_write_speaker_allocation()
67 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce3_2_afmt_dp_write_speaker_allocation()
118 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); in dce3_2_afmt_write_sad_regs()
H A Devergreen_hdmi.c123 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); in dce4_afmt_write_latency_fields()
143 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce4_afmt_hdmi_write_speaker_allocation()
163 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce4_afmt_dp_write_speaker_allocation()
214 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); in evergreen_hdmi_write_sad_regs()
H A Dradeon_audio.h32 #define WREG32_ENDPOINT(block, reg, v) \ macro