Searched refs:WREG32_OR (Results 1 – 8 of 8) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | r600_hdmi.c | 235 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_avi_packet() 238 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_set_avi_packet() 352 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, in r600_set_vbi_packet() 374 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_set_audio_packet() 408 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); in r600_set_mute() 462 WREG32_OR(HDMI0_CONTROL + offset, in r600_hdmi_update_audio_settings() 470 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_hdmi_update_audio_settings() 497 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); in r600_hdmi_enable() 505 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); in r600_hdmi_enable() 513 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); in r600_hdmi_enable()
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H A D | dce3_1_afmt.c | 226 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in dce3_2_set_audio_packet() 230 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, in dce3_2_set_audio_packet() 241 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); in dce3_2_set_mute()
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H A D | evergreen_hdmi.c | 406 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, in dce4_set_audio_packet() 418 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); in dce4_set_mute() 443 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable() 483 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_dp_enable()
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H A D | evergreen.c | 1732 WREG32_OR(DC_HPDx_INT_CONTROL(hpd), DC_HPDx_INT_POLARITY); in evergreen_hpd_set_polarity() 4627 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); in evergreen_irq_ack() 4632 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); in evergreen_irq_ack() 4637 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], in evergreen_irq_ack()
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H A D | si.c | 6166 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); in si_irq_ack() 6171 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); in si_irq_ack()
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H A D | radeon.h | 2574 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) macro
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | vce_v3_0.c | 544 WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000); in vce_v3_0_mc_resume()
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H A D | amdgpu.h | 1655 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) macro
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