Searched refs:WREG32_PCIE (Results 1 – 13 of 13) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | cik.c | 1473 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable() 1477 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable() 1505 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable() 1559 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm() 1564 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm() 1569 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm() 1582 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm() 1642 WREG32_PCIE(ixPCIE_LC_CNTL2, data); in cik_program_aspm() 1679 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm() 1687 WREG32_PCIE(ixPCIE_CNTL2, data); in cik_program_aspm() [all …]
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H A D | nbio_v6_1.c | 172 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating() 192 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep() 272 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v6_1_init_registers()
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H A D | nbio_v7_0.c | 161 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating() 203 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_0_update_medium_grain_light_sleep()
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H A D | amdgpu_cgs.c | 93 return WREG32_PCIE(index, value); in amdgpu_cgs_write_ind_register()
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H A D | amdgpu_debugfs.c | 285 WREG32_PCIE(*pos, value); in amdgpu_debugfs_regs_pcie_write()
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H A D | gmc_v7_0.c | 869 WREG32_PCIE(ixPCIE_CNTL2, data); in gmc_v7_0_enable_bif_mgls()
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H A D | vi.c | 1289 WREG32_PCIE(ixPCIE_CNTL2, data); in vi_update_bif_medium_grain_light_sleep()
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H A D | amdgpu.h | 1632 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) macro
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/dragonfly/sys/dev/drm/radeon/ |
H A D | r300.c | 88 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush() 158 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable() 161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable() 162 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable() 163 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable() 170 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); in rv370_pcie_gart_enable() 174 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable() 187 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); in rv370_pcie_gart_disable() 188 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); in rv370_pcie_gart_disable() 189 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_disable() [all …]
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H A D | si.c | 5568 WREG32_PCIE(PCIE_CNTL2, data); in si_enable_bif_mgls() 7271 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm() 7438 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
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H A D | rv6xx_dpm.c | 136 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv6xx_enable_pll_sleep_in_l1()
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H A D | rv770_dpm.c | 131 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv770_enable_pll_sleep_in_l1()
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H A D | radeon.h | 2549 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) macro
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