Home
last modified time | relevance | path

Searched refs:WREG32_PCIE (Results 1 – 13 of 13) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dcik.c1473 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1477 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1505 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1559 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm()
1564 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm()
1569 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm()
1582 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm()
1642 WREG32_PCIE(ixPCIE_LC_CNTL2, data); in cik_program_aspm()
1679 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm()
1687 WREG32_PCIE(ixPCIE_CNTL2, data); in cik_program_aspm()
[all …]
H A Dnbio_v6_1.c172 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating()
192 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep()
272 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v6_1_init_registers()
H A Dnbio_v7_0.c161 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating()
203 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_0_update_medium_grain_light_sleep()
H A Damdgpu_cgs.c93 return WREG32_PCIE(index, value); in amdgpu_cgs_write_ind_register()
H A Damdgpu_debugfs.c285 WREG32_PCIE(*pos, value); in amdgpu_debugfs_regs_pcie_write()
H A Dgmc_v7_0.c869 WREG32_PCIE(ixPCIE_CNTL2, data); in gmc_v7_0_enable_bif_mgls()
H A Dvi.c1289 WREG32_PCIE(ixPCIE_CNTL2, data); in vi_update_bif_medium_grain_light_sleep()
H A Damdgpu.h1632 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) macro
/dragonfly/sys/dev/drm/radeon/
H A Dr300.c88 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()
158 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable()
162 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
163 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
170 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); in rv370_pcie_gart_enable()
174 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
187 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); in rv370_pcie_gart_disable()
188 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); in rv370_pcie_gart_disable()
189 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_disable()
[all …]
H A Dsi.c5568 WREG32_PCIE(PCIE_CNTL2, data); in si_enable_bif_mgls()
7271 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
7438 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
H A Drv6xx_dpm.c136 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv6xx_enable_pll_sleep_in_l1()
H A Drv770_dpm.c131 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv770_enable_pll_sleep_in_l1()
H A Dradeon.h2549 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) macro