Searched refs:WREG32_PLL_P (Results 1 – 5 of 5) sorted by relevance
| /dragonfly/sys/dev/drm/radeon/ |
| H A D | radeon_legacy_crtc.c | 231 WREG32_PLL_P(RADEON_PPLL_REF_DIV, in radeon_pll_write_update()
258 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, in radeon_pll2_write_update()
867 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, in radeon_set_pll()
871 WREG32_PLL_P(RADEON_P2PLL_CNTL, in radeon_set_pll()
883 WREG32_PLL_P(RADEON_P2PLL_DIV_0, in radeon_set_pll()
887 WREG32_PLL_P(RADEON_P2PLL_DIV_0, in radeon_set_pll()
896 WREG32_PLL_P(RADEON_P2PLL_CNTL, in radeon_set_pll()
951 WREG32_PLL_P(RADEON_PPLL_CNTL, in radeon_set_pll()
988 WREG32_PLL_P(RADEON_PPLL_DIV_3, in radeon_set_pll()
992 WREG32_PLL_P(RADEON_PPLL_DIV_3, in radeon_set_pll()
[all …]
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| H A D | radeon_legacy_tv.c | 770 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); in radeon_legacy_tv_mode_set()
772 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); in radeon_legacy_tv_mode_set()
776 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); in radeon_legacy_tv_mode_set()
781 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); in radeon_legacy_tv_mode_set()
782 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); in radeon_legacy_tv_mode_set()
784 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); in radeon_legacy_tv_mode_set()
785 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); in radeon_legacy_tv_mode_set()
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| H A D | radeon_legacy_encoders.c | 109 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); in radeon_legacy_lvds_update()
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| H A D | radeon.h | 2575 #define WREG32_PLL_P(reg, val, mask) \ macro
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu.h | 1656 #define WREG32_PLL_P(reg, val, mask) \ macro
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