Searched refs:WREG32_RCU (Results 1 – 3 of 3) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | sumo_smc.c | 81 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4), in sumo_initialize_m3_arb() 85 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4), in sumo_initialize_m3_arb() 89 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4), in sumo_initialize_m3_arb() 123 WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param); in sumo_smu_notify_alt_vddnb_change() 157 WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value); in sumo_enable_boost_timer() 158 WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin); in sumo_enable_boost_timer() 159 WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin); in sumo_enable_boost_timer() 160 WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit); in sumo_enable_boost_timer() 161 WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg); in sumo_enable_boost_timer() 205 WREG32_RCU(regoffset, sclk_dpm_tdp_limit); in sumo_set_tdp_limit() [all …]
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H A D | sumo_dpm.c | 188 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210); in sumo_gfx_powergating_initialize() 189 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010); in sumo_gfx_powergating_initialize() 191 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210); in sumo_gfx_powergating_initialize() 192 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98); in sumo_gfx_powergating_initialize() 203 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); in sumo_gfx_powergating_initialize() 208 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl); in sumo_gfx_powergating_initialize() 213 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl); in sumo_gfx_powergating_initialize() 218 WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl); in sumo_gfx_powergating_initialize() 221 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02); in sumo_gfx_powergating_initialize() 233 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl); in sumo_gfx_powergating_initialize() [all …]
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H A D | radeon.h | 2555 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) macro
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