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Searched refs:_MASKED_BIT_ENABLE (Results 1 – 13 of 13) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_ringbuffer.c451 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in intel_ring_setup_status_page()
466 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); in stop_ring()
667 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in init_render_ring()
676 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in init_render_ring()
682 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); in init_render_ring()
687 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | in init_render_ring()
688 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); in init_render_ring()
701 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in init_render_ring()
1717 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); in gen6_bsd_submit_request()
H A Dintel_pm.c379 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()
390 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : in _intel_set_memory_cxsr()
7276 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in cherryview_enable_rc6()
7366 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in valleyview_enable_rc6()
8676 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); in hsw_init_clock_gating()
8718 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
8722 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
8793 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | in vlv_init_clock_gating()
8805 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in vlv_init_clock_gating()
9452 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
[all …]
H A Dintel_engine_cs.c846 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
978 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); in gen9_init_workarounds()
1119 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); in gen9_init_workarounds()
1231 _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE)); in bxt_init_workarounds()
1325 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); in cnl_init_workarounds()
H A Dintel_huc.c140 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA)); in huc_ucode_xfer()
H A Dintel_guc_fw.c154 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); in guc_ucode_xfer_dma()
H A Dintel_lrc.c1467 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); in gen8_init_common_ring()
1513 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in gen8_init_render_ring()
1515 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in gen8_init_render_ring()
2123 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | in execlists_init_reg_state()
H A Dintel_uncore.c1146 dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); in intel_uncore_fw_domains_init()
1394 I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING)); in gen3_stop_engine()
1696 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); in gen8_reset_engine_start()
H A Di915_gem_context.c641 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
H A Di915_guc_submission.c1040 irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); in guc_interrupts_capture()
H A Di915_gem_gtt.c1777 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); in gen8_ppgtt_enable()
1802 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen7_ppgtt_enable()
1820 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
H A Di915_gem.c5149 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()
5151 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()
5153 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in i915_gem_init_swizzling()
H A Di915_perf.c1682 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
H A Di915_reg.h171 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro