Searched refs:_MASKED_FIELD (Results 1 – 5 of 5) sorted by relevance
/dragonfly/sys/dev/drm/i915/ |
H A D | i915_guc_submission.c | 1086 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER); in guc_interrupts_release()
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H A D | intel_engine_cs.c | 852 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
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H A D | intel_lrc.c | 922 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8), in intel_lrc_irq_handler()
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H A D | intel_pm.c | 8367 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); in gen6_init_clock_gating() 8672 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); in hsw_init_clock_gating() 8766 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); in ivb_init_clock_gating() 8843 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); in vlv_init_clock_gating()
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H A D | i915_reg.h | 162 #define _MASKED_FIELD(mask, value) ({ \ macro 171 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 172 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
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