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Searched refs:bankw (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Devergreen_cs.c175 unsigned bankw; member
346 switch (surf->bankw) { in evergreen_surface_value_conv_check()
347 case 0: surf->bankw = 1; break; in evergreen_surface_value_conv_check()
348 case 1: surf->bankw = 2; break; in evergreen_surface_value_conv_check()
349 case 2: surf->bankw = 4; break; in evergreen_surface_value_conv_check()
350 case 3: surf->bankw = 8; break; in evergreen_surface_value_conv_check()
485 surf.bankw, surf.bankh, in evergreen_cs_track_validate_cb()
921 surf.bankw, surf.bankh, in evergreen_cs_track_validate_texture()
1188 DB_BANK_WIDTH(bankw) | in evergreen_cs_handle_reg()
1452 CB_BANK_WIDTH(bankw) | in evergreen_cs_handle_reg()
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H A Dradeon_object.c680 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local
682 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
687 switch (bankw) { in radeon_bo_set_tiling_flags()
H A Devergreen.c1096 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument
1100 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields()
1104 switch (*bankw) { in evergreen_tiling_fields()
1106 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break; in evergreen_tiling_fields()
1107 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break; in evergreen_tiling_fields()
1108 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break; in evergreen_tiling_fields()
1109 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break; in evergreen_tiling_fields()
H A Datombios_crtc.c1154 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local
1269 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1335 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); in dce4_crtc_do_set_base()
H A Dradeon.h357 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1952 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
1954 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1965 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); in dce_v10_0_crtc_do_set_base()
H A Ddce_v11_0.c1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v11_0_crtc_do_set_base() local
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2007 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); in dce_v11_0_crtc_do_set_base()
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c2083 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in fill_plane_attributes_from_fb() local
2085 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_plane_attributes_from_fb()
2096 plane_state->tiling_info.gfx8.bank_width = bankw; in fill_plane_attributes_from_fb()