/dragonfly/sys/dev/raid/twe/ |
H A D | twe_compat.h | 59 #define TWE_CONTROL(sc, val) bus_write_4((sc)->twe_io, 0x0, (u_int32_t)val) 61 #define TWE_COMMAND_QUEUE(sc, val) bus_write_4((sc)->twe_io, 0x8, (u_int32_t)val)
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/dragonfly/sys/dev/agp/ |
H A D | intel-gtt.c | 773 bus_write_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2, pgetbl_ctl2); in agp_gen5_adjust_pgtbl_size() 779 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgetbl_ctl); in agp_gen5_adjust_pgtbl_size() 825 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); in agp_i830_install_gatt() 905 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); in agp_i830_deinstall_gatt() 940 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, in agp_i810_resume() 1003 bus_write_4(sc->sc_res[0], index * 4, pte); in agp_i915_write_gtt() 1026 bus_write_4(sc->sc_res[0], index * 4 + (512 * 1024), pte); in agp_i965_write_gtt() 1049 bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte); in agp_g4x_write_gtt() 1294 bus_write_4(sc->sc_res[0], in agp_i810_bind_memory() 1693 bus_write_4(sc->sc_res[0], GFX_FLSH_CNTL, 1); in intel_enable_gtt() [all …]
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/dragonfly/sys/dev/misc/ichwd/ |
H A D | ichwd.c | 252 bus_write_4((sc)->tco_res, (off), (val)) 254 bus_write_4((sc)->smi_res, (off), (val)) 256 bus_write_4((sc)->gcs_res, (off), (val))
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/dragonfly/sys/dev/crypto/tpm/ |
H A D | tpm20.h | 169 bus_write_4(sc->mem_res, off, val); in WR4()
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/dragonfly/sys/dev/misc/amdsbwd/ |
H A D | amdsbwd.c | 152 bus_write_4(sc->res_ctrl, 0, val); in wdctrl_write() 164 bus_write_4(sc->res_count, 0, val); in wdcount_write()
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/dragonfly/sys/bus/pci/ |
H A D | pci.c | 1436 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); in pci_setup_msix_vector() 1437 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); in pci_setup_msix_vector() 1438 bus_write_4(msix->msix_table_res, offset + 8, data); in pci_setup_msix_vector() 1456 bus_write_4(msix->msix_table_res, offset, val); in pci_mask_msix_vector() 1472 bus_write_4(msix->msix_table_res, offset, val); in pci_unmask_msix_vector() 2841 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); in ohci_early_takeover() 2850 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); in ohci_early_takeover() 2853 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); in ohci_early_takeover() 2934 bus_write_4(res, offs + EHCI_USBINTR, 0); in ehci_early_takeover() 3009 bus_write_4(res, offs + XHCI_USBCMD, 0); in xhci_early_takeover()
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/dragonfly/sys/dev/netif/bge/ |
H A D | if_bgevar.h | 88 bus_write_4(sc->bge_res2, reg, val)
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/dragonfly/sys/dev/disk/sdhci/ |
H A D | sdhci_acpi.c | 123 bus_write_4(sc->mem_res, off, val); in sdhci_acpi_write_4()
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H A D | sdhci_pci.c | 214 bus_write_4(sc->mem_res[slot->num], off, val); in sdhci_pci_write_4()
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/dragonfly/sys/dev/netif/bnx/ |
H A D | if_bnxvar.h | 88 bus_write_4(sc->bnx_res2, reg, val)
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/dragonfly/sys/bus/gpio/gpio_intel/ |
H A D | gpio_cherryview.c | 176 bus_write_4(sc->mem_res, offset, val); in chvgpio_write()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | amdgpu_device.c | 240 bus_write_4(adev->rio_mem, (mmMM_INDEX * 4), (reg * 4)); in amdgpu_io_rreg() 261 bus_write_4(adev->rio_mem, (reg * 4), v); in amdgpu_io_wreg() 263 bus_write_4(adev->rio_mem, (mmMM_INDEX * 4), (reg * 4)); in amdgpu_io_wreg() 264 bus_write_4(adev->rio_mem, (mmMM_DATA * 4), v); in amdgpu_io_wreg()
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/dragonfly/sys/dev/virtual/virtio/pci/ |
H A D | virtio_pci.c | 164 #define vtpci_write_config_4(sc, o, v) bus_write_4((sc)->vtpci_res, (o), (v))
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/dragonfly/sys/sys/ |
H A D | bus.h | 639 #define bus_write_4(r, o, v) \ macro
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/dragonfly/sys/dev/virtual/vmware/pvscsi/ |
H A D | pvscsi.c | 269 bus_write_4(sc->mm_res, offset, val); in pvscsi_reg_write()
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/dragonfly/sys/dev/disk/sym/ |
H A D | sym_hipd.c | 874 #define OUTL_OFF(o, v) bus_write_4(np->io_res, (o), (v)) 884 #define OUTL_OFF(o, v) bus_write_4(np->mmio_res, (o), (v))
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